On Fri, Aug 7, 2020 at 2:36 AM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 8/6/20 3:46 AM, frank.ch...@sifive.com wrote:
> > + float flmul;
>
> int8_t? It seems weird that the translator wouldn't also use...
>
It was kept for vector check functions.
However, I've removed float flmul and changed my
vector check functions to something like:
> static bool vext_check_sss(DisasContext *s, int vd, int vs1,
> int vs2, int vm, bool is_vs1)
> {
> bool ret = require_vm(vm, vd);
> if (s->lmul > 0) {
> ret &= require_align(vd, 1 << s->lmul) &&
> require_align(vs2, 1 << s->lmul);
> if (is_vs1) {
> ret &= require_align(vs1, 1 << s->lmul);
> }
> }
> return ret;
> }
which use shifts to check the alignment/noover of vector registers.
The parameters passed to require_align() and require_noover()
are also changed to const uint8_t type so that the shifted value can be
wrapped within 8-bits.
int8_t lmul in DisasContext is also encoded:
ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3);
> > +/*
> > + * Encode LMUL to lmul as following:
> > + * LMUL vlmul lmul
> > + * 1 000 0
> > + * 2 001 1
> > + * 4 010 2
> > + * 8 011 3
> > + * - 100 -
> > + * 1/8 101 -3
> > + * 1/4 110 -2
> > + * 1/2 111 -1
> > + */
> > +static inline int32_t vext_lmul(uint32_t desc)
> > {
> > - return FIELD_EX32(simd_data(desc), VDATA, LMUL);
> > + uint32_t lmul = FIELD_EX32(simd_data(desc), VDATA, LMUL);
> > + return (int8_t)(lmul << 5) >> 5;
> > }
>
> ... this encoding?
>
> Oh, and sextract32(lmul, 0, 3) instead of those shifts.
>
OK~
>
>
> r~
>
Thanks
Frank Chang
