Hi Anup, On 8/17/20 11:30 AM, Bin Meng wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the > content is safe > > Hi Anup, > > On Sat, Aug 15, 2020 at 1:44 AM Anup Patel <a...@brainfault.org> wrote: >> On Fri, Aug 14, 2020 at 10:12 PM Bin Meng <bmeng...@gmail.com> wrote: >>> From: Bin Meng <bin.m...@windriver.com> >>> >>> This adds support for Microchip PolarFire SoC Icicle Kit board. >>> The Icicle Kit board integrates a PolarFire SoC, with one SiFive's >>> E51 plus four U54 cores and many on-chip peripherals and an FPGA. >> Nice Work !!! This is very helpful. > Thanks! > >> The Microchip HSS is quite convoluted. It has: >> 1. DDR Init >> 2. Boot device support >> 3. SBI support using OpenSBI as library >> 4. Simple TEE support >> >> I think point 1) and 2) above should be part of U-Boot SPL. >> The point 3) can be OpenSBI FW_DYNAMIC. >> >> Lastly,for point 4), we are working on a new OpenSBI feature using >> which we can run independent Secure OS and Non-Secure OS using >> U-Boot_SPL+OpenSBI (for both SiFive Unleashed and Microchip >> PolarFire). >> >> Do you have plans for adding U-Boot SPL support for this board ?? > + Cyril Jean from Microchip > > I will have to leave this question to Cyril to comment. > I currently do not have a plan to support U-Boot SPL. The idea of the HSS is to contain all the silicon specific initialization and configuration code within the HSS before jumping to U-Boot S-mode. I would rather keep all this within the HSS for the time being. I would wait until we reach production silicon before attempting to move this to U-Boot SPL as the HSS is likely to contain some opaque silicon related changes for another while.
Regards, Cyril.
