From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com> When the CPU has exceptions disabled, avoid unwinding CPU state and clobbering registers if we're not going to raise any exception.
Signed-off-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> --- target/microblaze/op_helper.c | 19 +++++++------------ 1 file changed, 7 insertions(+), 12 deletions(-) diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index 13ac476199..190cd96c6a 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -483,22 +483,17 @@ void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, cpu = MICROBLAZE_CPU(cs); env = &cpu->env; - cpu_restore_state(cs, retaddr, true); if (!(env->sregs[SR_MSR] & MSR_EE)) { return; } - env->sregs[SR_EAR] = addr; - if (access_type == MMU_INST_FETCH) { - if (cpu->cfg.iopb_bus_exception) { - env->sregs[SR_ESR] = ESR_EC_INSN_BUS; - helper_raise_exception(env, EXCP_HW_EXCP); - } - } else { - if (cpu->cfg.dopb_bus_exception) { - env->sregs[SR_ESR] = ESR_EC_DATA_BUS; - helper_raise_exception(env, EXCP_HW_EXCP); - } + if ((access_type == MMU_INST_FETCH && cpu->cfg.iopb_bus_exception) || + (access_type != MMU_INST_FETCH && cpu->cfg.dopb_bus_exception)) { + cpu_restore_state(cs, retaddr, true); + env->sregs[SR_ESR] = access_type == MMU_INST_FETCH ? + ESR_EC_INSN_BUS : ESR_EC_DATA_BUS; + env->sregs[SR_EAR] = addr; + helper_raise_exception(env, EXCP_HW_EXCP); } } #endif -- 2.25.1