Le ven. 28 août 2020 16:25, Richard Henderson <richard.hender...@linaro.org>
a écrit :
> Continue eliminating the sregs array in favor of individual members.
> Does not correct the width of FSR, yet.
>
> Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
>
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
---
> target/microblaze/cpu.h | 1 +
> linux-user/microblaze/cpu_loop.c | 4 ++--
> target/microblaze/gdbstub.c | 4 ++--
> target/microblaze/op_helper.c | 8 ++++----
> target/microblaze/translate.c | 6 ++++--
> 5 files changed, 13 insertions(+), 10 deletions(-)
>
> diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
> index 7d94af43ed..bcafef99b0 100644
> --- a/target/microblaze/cpu.h
> +++ b/target/microblaze/cpu.h
> @@ -240,6 +240,7 @@ struct CPUMBState {
> uint64_t msr;
> uint64_t ear;
> uint64_t esr;
> + uint64_t fsr;
> uint64_t sregs[14];
> float_status fp_status;
> /* Stack protectors. Yes, it's a hw feature. */
> diff --git a/linux-user/microblaze/cpu_loop.c
> b/linux-user/microblaze/cpu_loop.c
> index c10e3e0261..da5e98b784 100644
> --- a/linux-user/microblaze/cpu_loop.c
> +++ b/linux-user/microblaze/cpu_loop.c
> @@ -96,10 +96,10 @@ void cpu_loop(CPUMBState *env)
> case ESR_EC_FPU:
> info.si_signo = TARGET_SIGFPE;
> info.si_errno = 0;
> - if (env->sregs[SR_FSR] & FSR_IO) {
> + if (env->fsr & FSR_IO) {
> info.si_code = TARGET_FPE_FLTINV;
> }
> - if (env->sregs[SR_FSR] & FSR_DZ) {
> + if (env->fsr & FSR_DZ) {
> info.si_code = TARGET_FPE_FLTDIV;
> }
> info._sifields._sigfault._addr = 0;
> diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c
> index 05e22f233d..2634ce49fc 100644
> --- a/target/microblaze/gdbstub.c
> +++ b/target/microblaze/gdbstub.c
> @@ -71,7 +71,7 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray
> *mem_buf, int n)
> val = env->esr;
> break;
> case GDB_FSR:
> - val = env->sregs[SR_FSR];
> + val = env->fsr;
> break;
> case GDB_BTR:
> val = env->sregs[SR_BTR];
> @@ -127,7 +127,7 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t
> *mem_buf, int n)
> env->esr = tmp;
> break;
> case GDB_FSR:
> - env->sregs[SR_FSR] = tmp;
> + env->fsr = tmp;
> break;
> case GDB_BTR:
> env->sregs[SR_BTR] = tmp;
> diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c
> index f01cf9be64..ae57d45536 100644
> --- a/target/microblaze/op_helper.c
> +++ b/target/microblaze/op_helper.c
> @@ -175,19 +175,19 @@ static void update_fpu_flags(CPUMBState *env, int
> flags)
> int raise = 0;
>
> if (flags & float_flag_invalid) {
> - env->sregs[SR_FSR] |= FSR_IO;
> + env->fsr |= FSR_IO;
> raise = 1;
> }
> if (flags & float_flag_divbyzero) {
> - env->sregs[SR_FSR] |= FSR_DZ;
> + env->fsr |= FSR_DZ;
> raise = 1;
> }
> if (flags & float_flag_overflow) {
> - env->sregs[SR_FSR] |= FSR_OF;
> + env->fsr |= FSR_OF;
> raise = 1;
> }
> if (flags & float_flag_underflow) {
> - env->sregs[SR_FSR] |= FSR_UF;
> + env->fsr |= FSR_UF;
> raise = 1;
> }
> if (raise
> diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
> index 411c7b6e49..c58c49ea8f 100644
> --- a/target/microblaze/translate.c
> +++ b/target/microblaze/translate.c
> @@ -1810,7 +1810,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int
> flags)
> "debug=%x imm=%x iflags=%x fsr=%" PRIx64 " "
> "rbtr=%" PRIx64 "\n",
> env->msr, env->esr, env->ear,
> - env->debug, env->imm, env->iflags, env->sregs[SR_FSR],
> + env->debug, env->imm, env->iflags, env->fsr,
> env->sregs[SR_BTR]);
> qemu_fprintf(f, "btaken=%d btarget=%" PRIx64 " mode=%s(saved=%s) "
> "eip=%d ie=%d\n",
> @@ -1877,8 +1877,10 @@ void mb_tcg_init(void)
> tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear),
> "rear");
> cpu_SR[SR_ESR] =
> tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, esr),
> "resr");
> + cpu_SR[SR_FSR] =
> + tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, fsr),
> "rfsr");
>
> - for (i = SR_ESR + 1; i < ARRAY_SIZE(cpu_SR); i++) {
> + for (i = SR_FSR + 1; i < ARRAY_SIZE(cpu_SR); i++) {
> cpu_SR[i] = tcg_global_mem_new_i64(cpu_env,
> offsetof(CPUMBState, sregs[i]),
> special_regnames[i]);
> --
> 2.25.1
>
>
>
