On 9/30/20 9:40 AM, Igor Mammedov wrote: > On Mon, 28 Sep 2020 19:15:23 +0200 > Philippe Mathieu-Daudé <f4...@amsat.org> wrote: > >> All the MIPS cores emulated by QEMU provides the Coproc#0 >> 'Count' register which can be used as a free running timer. >> >> Since it's introduction in 2005 this timer uses a fixed >> frequency of 100 MHz (for a CPU freq of 200 MHz). >> While this is not an issue with Linux guests, it makes >> some firmwares behave incorrectly. >> >> The Clock API allow propagating clocks. It is particularly >> useful when hardware dynamicly changes clock frequencies. >> >> To be able to model such MIPS hardware, we need to refactor >> the MIPS hardware code to handle clocks. >> >> This series is organized as follow: >> >> - let all CPU have an input clock, >> - MIPS CPU get an input clock >> - when the clock is changed, CP0 timer is updated >> - set correct CPU frequencies to all boards >> - do not allow MIPS CPU without input clock > > is this clock an integral part of MIPS cpus or it's an external device?
CPU cores are clocked via an external clock. This clock can be on the board (from a crystal oscillator to complex PLL) or on-chip for some system-on-chip. In all the (current) QEMU MIPS machines it is external although. Regards, Phil.