On Tue, Oct 13, 2020 at 12:11:20PM +0000, Zengtao (B) wrote: > Cc valentin > > > -----Original Message----- > > From: Qemu-devel > > [mailto:qemu-devel-bounces+prime.zeng=hisilicon....@nongnu.org] > > On Behalf Of Ying Fang > > Sent: Thursday, September 17, 2020 11:20 AM > > To: qemu-devel@nongnu.org > > Cc: peter.mayd...@linaro.org; drjo...@redhat.com; Zhanghailiang; > > Chenzhendong (alex); shannon.zha...@gmail.com; > > qemu-...@nongnu.org; alistair.fran...@wdc.com; fangying; > > imamm...@redhat.com > > Subject: [RFC PATCH 00/12] hw/arm/virt: Introduce cpu and cache > > topology support > > > > An accurate cpu topology may help improve the cpu scheduler's > > decision > > making when dealing with multi-core system. So cpu topology > > description > > is helpful to provide guest with the right view. Cpu cache information > > may > > also have slight impact on the sched domain, and even userspace > > software > > may check the cpu cache information to do some optimizations. Thus > > this patch > > series is posted to provide cpu and cache topology support for arm. > > > > To make the cpu topology consistent with MPIDR, an vcpu ioctl > > For aarch64, the cpu topology don't depends on the MPDIR. > See https://patchwork.kernel.org/patch/11744387/ >
The topology should not be inferred from the MPIDR Aff fields, but MPIDR is the CPU identifier. When describing a topology with ACPI or DT the CPU elements in the topology description must map to actual CPUs. MPIDR is that mapping link. KVM currently determines what the MPIDR of a VCPU is. If KVM userspace is going to determine the VCPU topology, then it also needs control over the MPIDR values, otherwise it becomes quite messy trying to get the mapping right. Thanks, drew
