On Tue, Oct 13, 2020 at 10:31 AM Georg Kotheimer
<georg.kothei...@kernkonzept.com> wrote:
>
> The hstatus.GVA bit was not set if the faulting guest virtual address
> was zero.
>
> Signed-off-by: Georg Kotheimer <georg.kothei...@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> target/riscv/cpu_helper.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 904899054d..c5852ce1b7 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -852,6 +852,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG);
> target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK;
> target_ulong deleg = async ? env->mideleg : env->medeleg;
> + bool write_tval = false;
> target_ulong tval = 0;
> target_ulong htval = 0;
> target_ulong mtval2 = 0;
> @@ -873,6 +874,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> case RISCV_EXCP_INST_PAGE_FAULT:
> case RISCV_EXCP_LOAD_PAGE_FAULT:
> case RISCV_EXCP_STORE_PAGE_FAULT:
> + write_tval = true;
> tval = env->badaddr;
> break;
> default:
> @@ -904,7 +906,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> target_ulong hdeleg = async ? env->hideleg : env->hedeleg;
>
> if ((riscv_cpu_virt_enabled(env) ||
> - riscv_cpu_two_stage_lookup(env)) && tval) {
> + riscv_cpu_two_stage_lookup(env)) && write_tval) {
> /*
> * If we are writing a guest virtual address to stval, set
> * this to 1. If we are trapping to VS we will set this to 0
> --
> 2.25.1
>
>
