QEMU does not model caches, so there is not much to do with the Invalidate/Writeback opcodes. Make it explicit adding a comment.
Suggested-by: Jiaxun Yang <jiaxun.y...@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4...@amsat.org> Reviewed-by: Richard Henderson <richard.hender...@linaro.org> Reviewed-by: Jiaxun Yang <jiaxun.y...@flygoat.com> Message-Id: <20200813181527.22551-3-f4...@amsat.org> --- target/mips/op_helper.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index c15f5c07761..2496d1dd718 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -1586,6 +1586,11 @@ void helper_cache(CPUMIPSState *env, target_ulong addr, uint32_t op) memory_region_dispatch_read(env->itc_tag, index, &env->CP0_TagLo, MO_64, MEMTXATTRS_UNSPECIFIED); break; + case 0b000: /* Index Invalidate */ + case 0b100: /* Hit Invalidate */ + case 0b110: /* Hit Writeback */ + /* no-op */ + break; default: break; } -- 2.26.2