Support devicetree CPU cache information descriptions
Signed-off-by: Ying Fang <fangyi...@huawei.com>
---
hw/arm/virt.c | 92 +++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 92 insertions(+)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index d23b941020..adcfa52854 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -346,6 +346,89 @@ static void fdt_add_timer_nodes(const VirtMachineState
*vms)
GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags);
}
+static void fdt_add_l3cache_nodes(const VirtMachineState *vms)
+{
+ int i;
+ const MachineState *ms = MACHINE(vms);
+ ARMCPU *cpu = ARM_CPU(first_cpu);
+ unsigned int smp_cores = ms->smp.cores;
+ unsigned int sockets = ms->smp.max_cpus / smp_cores;
+
+ for (i = 0; i < sockets; i++) {
+ char *nodename = g_strdup_printf("/cpus/l3-cache%d", i);
+ qemu_fdt_add_subnode(vms->fdt, nodename);
+ qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cache");
+ qemu_fdt_setprop_string(vms->fdt, nodename, "cache-unified", "true");
+ qemu_fdt_setprop_cell(vms->fdt, nodename, "cache-level", 3);
+ qemu_fdt_setprop_cell(vms->fdt, nodename, "cache-size",
+ cpu->caches.l3_cache->size);
+ qemu_fdt_setprop_cell(vms->fdt, nodename, "cache-line-size",
+ cpu->caches.l3_cache->line_size);
+ qemu_fdt_setprop_cell(vms->fdt, nodename, "cache-sets",
+ cpu->caches.l3_cache->sets);
+ qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle",
+ qemu_fdt_alloc_phandle(vms->fdt));
+ g_free(nodename);
+ }
+}
+
+static void fdt_add_l2cache_nodes(const VirtMachineState *vms)
+{
+ int i, j;
+ const MachineState *ms = MACHINE(vms);
+ unsigned int smp_cores = ms->smp.cores;
+ signed int sockets = ms->smp.max_cpus / smp_cores;
+ ARMCPU *cpu = ARM_CPU(first_cpu);
+
+ for (i = 0; i < sockets; i++) {
+ char *next_path = g_strdup_printf("/cpus/l3-cache%d", i);
+ for (j = 0; j < smp_cores; j++) {
+ char *nodename = g_strdup_printf("/cpus/l2-cache%d",
+ i * smp_cores + j);
+ qemu_fdt_add_subnode(vms->fdt, nodename);
+ qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cache");
+ qemu_fdt_setprop_cell(vms->fdt, nodename, "cache-size",
+ cpu->caches.l2_cache->size);
+ qemu_fdt_setprop_cell(vms->fdt, nodename, "cache-line-size",
+ cpu->caches.l2_cache->line_size);
+ qemu_fdt_setprop_cell(vms->fdt, nodename, "cache-sets",
+ cpu->caches.l2_cache->sets);
+ qemu_fdt_setprop_phandle(vms->fdt, nodename,
+ "next-level-cache", next_path);
+ qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle",
+ qemu_fdt_alloc_phandle(vms->fdt));
+ g_free(nodename);
+ }
+ g_free(next_path);
+ }
+}
+
+static void fdt_add_l1cache_prop(const VirtMachineState *vms,
+ char *nodename, int cpu_index)
+{
+
+ ARMCPU *cpu = ARM_CPU(qemu_get_cpu(cpu_index));
+ CPUCaches caches = cpu->caches;
+
+ char *cachename = g_strdup_printf("/cpus/l2-cache%d", cpu_index);
+
+ qemu_fdt_setprop_cell(vms->fdt, nodename, "d-cache-size",
+ caches.l1d_cache->size);
+ qemu_fdt_setprop_cell(vms->fdt, nodename, "d-cache-line-size",
+ caches.l1d_cache->line_size);
+ qemu_fdt_setprop_cell(vms->fdt, nodename, "d-cache-sets",
+ caches.l1d_cache->sets);
+ qemu_fdt_setprop_cell(vms->fdt, nodename, "i-cache-size",
+ caches.l1i_cache->size);
+ qemu_fdt_setprop_cell(vms->fdt, nodename, "i-cache-line-size",
+ caches.l1i_cache->line_size);
+ qemu_fdt_setprop_cell(vms->fdt, nodename, "i-cache-sets",
+ caches.l1i_cache->sets);
+ qemu_fdt_setprop_phandle(vms->fdt, nodename, "next-level-cache",
+ cachename);
+ g_free(cachename);
+}
+
static void fdt_add_cpu_nodes(const VirtMachineState *vms)
{
int cpu;
@@ -379,6 +462,11 @@ static void fdt_add_cpu_nodes(const VirtMachineState *vms)
qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#address-cells", addr_cells);
qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#size-cells", 0x0);
+ if (!vmc->ignore_cpu_topology) {
+ fdt_add_l3cache_nodes(vms);
+ fdt_add_l2cache_nodes(vms);
+ }
+
for (cpu = ms->smp.cpus - 1; cpu >= 0; cpu--) {
char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
@@ -408,6 +496,10 @@ static void fdt_add_cpu_nodes(const VirtMachineState *vms)
ms->possible_cpus->cpus[cs->cpu_index].props.node_id);
}
+ if (!vmc->ignore_cpu_topology) {
+ fdt_add_l1cache_prop(vms, nodename, cpu);
+ }
+
if (ms->smp.cpus > 1 && !vmc->ignore_cpu_topology) {
qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle",
qemu_fdt_alloc_phandle(vms->fdt));
--
2.23.0
