On 10/24/20 8:00 AM, Alistair Francis wrote: >>>> +#define RISCV_EXCP_SEMIHOST 0x10 >>> >>> I don't see this in the RISC-V spec, it seems to just be reserved, not >>> for semihosting. >> >> Hrm. It's entirely an internal implementation detail in QEMU and matches >> how semihosting works in the ARM implementation -- the presence of the >> semihosting breakpoint raises this exception which is then handled in >> the usual exception processing path. > > It's not fully internal though. Someone running with the `-d int` > command line argument will see these exceptions, which don't > correspond to anything in the spec. > > Is there some way we could at least convey that information to users?
This is no different to EXCP_DEBUG, really, which is also internal to qemu but user-visible in the same way. Just adjust the logging in riscv_cpu_do_interrupt. r~
