On 11/6/20 3:32 AM, Alistair Francis wrote: > After claiming the interrupt by reading the claim register we want to > clear the register to make sure the interrupt doesn't appear at the next > read. > > This matches the documentation for the claim register as it clears the > pending bit (which we already do): > https://docs.opentitan.org/hw/ip/rv_plic/doc/index.html
"When an interrupt is claimed by a target the relevant bit of IP is cleared." Correct. Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org> > > This also matches the current hardware. > > Signed-off-by: Alistair Francis <alistair.fran...@wdc.com> > --- > hw/intc/ibex_plic.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/hw/intc/ibex_plic.c b/hw/intc/ibex_plic.c > index f49fa67c91..235e6b88ff 100644 > --- a/hw/intc/ibex_plic.c > +++ b/hw/intc/ibex_plic.c > @@ -139,6 +139,9 @@ static uint64_t ibex_plic_read(void *opaque, hwaddr addr, > /* Return the current claimed interrupt */ > ret = s->claim; > > + /* Clear the claimed interrupt */ > + s->claim = 0x00000000; > + > /* Update the interrupt status after the claim */ > ibex_plic_update(s); > } >
