On Fri, Nov 13, 2020 at 10:39:42AM +0100, Philippe Mathieu-Daudé wrote: > On 2/27/19 3:00 PM, Aleksandar Markovic wrote: > > From: Mateja Marjanovic <mateja.marjano...@rt-rk.com> > > > > Set up MMI code to be compiled only for TARGET_MIPS64. This is > > needed so that GPRs are 64 bit, and combined with MMI registers, > > they will form full 128 bit registers. > > > > Signed-off-by: Mateja Marjanovic <mateja.marjano...@rt-rk.com> > > Signed-off-by: Aleksandar Markovic <amarko...@wavecomp.com> > > Reviewed-by: Aleksandar Rikalo <arik...@wavecomp.com> > > Message-Id: <1551183797-13570-2-git-send-email-mateja.marjano...@rt-rk.com> > > --- > > target/mips/translate.c | 43 +++++++++++++++++++++++++++++++++++++++++-- > > 1 file changed, 41 insertions(+), 2 deletions(-) > ... > > > static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx) > > { > > int rs, rt, rd, sa; > > @@ -28796,10 +28828,11 @@ static void decode_opc(CPUMIPSState *env, > > DisasContext *ctx) > > decode_opc_special(env, ctx); > > break; > > case OPC_SPECIAL2: > > +#if defined(TARGET_MIPS64) > > if ((ctx->insn_flags & INSN_R5900) && (ctx->insn_flags & ASE_MMI)) > > { > > decode_mmi(env, ctx); > > This change is incorrect, you removed support for the > MADD[U] and MULT[U] instructions on TXx9 32-bit targets > (TX79 still works).
The 128-bit MMIs and R5900 specific registers are always valid on R5900 hardware regardless of 32- and 64-bit operation modes[1]. CP0.Status.UX isn't implemented[2]. In other MIPS ISA implementations, attempting to execute 64-bit operations in 32-bit user or supervisor mode may cause a reserved instruction exception. It would be wise to limit any R5900 specific psABIs, while permitting useful features such as the MMIs. GCC emits MULT[U] for R5900 o32. Fredrik References: [1] "EE Core User's Manual", version 6.0, Sony Computer Entertainment Inc., p. 107. [2] "TX System RISC TX79 Core Architecture" manual, revision 2.0, Toshiba Corporation, p. 4-16, https://wiki.qemu.org/File:C790.pdf