Kito Cheng <kito.ch...@gmail.com> writes:
> Hi Keith: > > Thanks for your reply, but it seems like we need some more modification in > linux-user/riscv/cpu_loop.c to enable that, I guess I should post that in > mail > rather than attachment :) > > Patch here: > > From 2f1eb5825a6dda177d3289106970eab05cb08445 Mon Sep 17 00:00:00 2001 > From: Kito Cheng <kito.ch...@sifive.com> > Date: Wed, 9 Dec 2020 14:24:51 +0800 > Subject: [PATCH] riscv: Add semihosting support for user mode > > This could make testing easier and ARM/AArch64 has support on > their linux user mode too, so I think it should be reasonable. > > Verified GCC testsuite with newlib/semihosting. > > Signed-off-by: Kito Cheng <kito.ch...@sifive.com> If the riscv linux-user maintainer is happy with it I'll take it through semihosting/next. It certainly has a use case in the ARM case. > --- > linux-user/riscv/cpu_loop.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c > index aa9e437875..9665dabb09 100644 > --- a/linux-user/riscv/cpu_loop.c > +++ b/linux-user/riscv/cpu_loop.c > @@ -23,6 +23,7 @@ > #include "qemu.h" > #include "cpu_loop-common.h" > #include "elf.h" > +#include "hw/semihosting/common-semi.h" > > void cpu_loop(CPURISCVState *env) > { > @@ -91,6 +92,10 @@ void cpu_loop(CPURISCVState *env) > sigcode = TARGET_SEGV_MAPERR; > sigaddr = env->badaddr; > break; > + case RISCV_EXCP_SEMIHOST: > + env->gpr[xA0] = do_common_semihosting(cs); > + env->pc += 4; > + break; > case EXCP_DEBUG: > gdbstep: > signum = TARGET_SIGTRAP; -- Alex Bennée