在 2020/12/16 下午6:59, Philippe Mathieu-Daudé 写道:
On 12/16/20 11:50 AM, Philippe Mathieu-Daudé wrote:
On 12/16/20 4:14 AM, Jiaxun Yang wrote:
在 2020/12/16 上午10:50, Jiaxun Yang 写道:
TBH I do think it doesn't sounds like a good idea to make 32-bit
and 64-bit different. In fact ISA_MIPS32R6 is always set for targets
with ISA_MIPS64R6.
We're treating MIPS64R6 as a superset of MIPS32R6, and ISA_MIPS3
is used to tell if a CPU supports 64-bit.
I suppose you are talking about the CPU definitions
(CPU_MIPS32R6/CPU_MIPS64R6).
Which is why I don't understand why they are 2 ISA_MIPS32R6/ISA_MIPS64R6
definitions.
My comment is about the ISA definitions:
#define ISA_MIPS32 0x0000000000000020ULL
#define ISA_MIPS32R2 0x0000000000000040ULL
#define ISA_MIPS64 0x0000000000000080ULL
#define ISA_MIPS64R2 0x0000000000000100ULL
#define ISA_MIPS32R3 0x0000000000000200ULL
#define ISA_MIPS64R3 0x0000000000000400ULL
#define ISA_MIPS32R5 0x0000000000000800ULL
#define ISA_MIPS64R5 0x0000000000001000ULL
#define ISA_MIPS32R6 0x0000000000002000ULL
#define ISA_MIPS64R6 0x0000000000004000ULL
Yes, as insn_flags is
/* MIPS Technologies "Release 1" */
#define CPU_MIPS32 (CPU_MIPS2 | ISA_MIPS32)
#define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64)
/* MIPS Technologies "Release 2" */
#define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2)
#define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2)
......
As you can see when you're set insn_flags to CPU_MIPS64R2 the ISA flags
for ISA_MIPS64R2 ISA_MIPS32R2 ISA_MIPS32 ISA_MIPS64 ISA_MIPS5
ISA_MIPS3 ISA_MIPS2 ISA_MIPS1 all get set as well.
So we may end up having four series of decodetrees for ISA
Series1: MIPS-II, MIPS32, MIPS32R2, MIPS32R5 (32bit "old" ISAs)
Series2: MIPS-III, MIPS64, MIPS64R2, MIPS64R5 (64bit "old" ISAs)
Series3: MIPS32R6 (32bit "new" ISAs)
Series4: MIPS64R6 (64bit "new" ISAs)
Something like that, I'm starting by converting the messier leaves
first, so the R6 and ASEs. My approach is from your "series4" to
"series1" last.
Sounds neat!
Thanks.
- Jiaxun
Regards,
Phil.
