Thank you for your remark here is the new patch:
Signed-off-by: Sylvain Pelissier <sylvain.peliss...@gmail.com>
---
target/riscv/cpu.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 254cd83f8b..ed4971978b 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -556,6 +556,18 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_END_OF_LIST(),
};
+static gchar *riscv_gdb_arch_name(CPUState *cs)
+{
+ RISCVCPU *cpu = RISCV_CPU(cs);
+ CPURISCVState *env = &cpu->env;
+
+ if (riscv_cpu_is_32bit(env)) {
+ return g_strdup("riscv:rv32");
+ } else {
+ return g_strdup("riscv:rv64");
+ }
+}
+
static void riscv_cpu_class_init(ObjectClass *c, void *data)
{
RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
@@ -591,6 +603,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void
*data)
/* For now, mark unmigratable: */
cc->vmsd = &vmstate_riscv_cpu;
#endif
+ cc->gdb_arch_name = riscv_gdb_arch_name;
#ifdef CONFIG_TCG
cc->tcg_initialize = riscv_translate_init;
cc->tlb_fill = riscv_cpu_tlb_fill;
--
2.25.1
Regards
Sylvain
On Tue, 29 Dec 2020 at 05:11, Bin Meng <bmeng...@gmail.com> wrote:
> On Thu, Dec 24, 2020 at 1:09 AM Sylvain Pelissier
> <sylvain.peliss...@gmail.com> wrote:
> >
> > Target description is not currently implemented in RISC-V architecture.
> Thus GDB won't set it properly when attached. The patch implements the
> target description response.
> >
> > Signed-off-by: Sylvain Pelissier <sylvain.peliss...@gmail.com>
> > ---
> > target/riscv/cpu.c | 10 ++++++++++
> > 1 file changed, 10 insertions(+)
> >
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > index 254cd83f8b..489d66038c 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -556,6 +556,15 @@ static Property riscv_cpu_properties[] = {
> > DEFINE_PROP_END_OF_LIST(),
> > };
> >
> > +static gchar *riscv_gdb_arch_name(CPUState *cs)
> > +{
> > + #ifdef TARGET_RISCV64
>
> Use riscv_cpu_is_32bit() instead of #ifdefs
>
> > + return g_strdup("riscv:rv64");
> > + #else
> > + return g_strdup("riscv:rv32");
> > + #endif
> > +}
> > +
> > static void riscv_cpu_class_init(ObjectClass *c, void *data)
> > {
> > RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
> > @@ -591,6 +600,7 @@ static void riscv_cpu_class_init(ObjectClass *c,
> void *data)
> > /* For now, mark unmigratable: */
> > cc->vmsd = &vmstate_riscv_cpu;
> > #endif
> > + cc->gdb_arch_name = riscv_gdb_arch_name;
> > #ifdef CONFIG_TCG
> > cc->tcg_initialize = riscv_translate_init;
> > cc->tlb_fill = riscv_cpu_tlb_fill;
> > --
>
> Regards,
> Bin
>
