On 11/30/2020 9:00 PM, Peter Maydell wrote:
On Mon, 9 Nov 2020 at 03:05, Ying Fang <fangyi...@huawei.com> wrote:
Add the CPUCacheInfo structure to hold cpu cache information for ARM cpus.
A classic three level cache topology is used here. The default cache
capacity is given and userspace can overwrite these values.
Signed-off-by: Ying Fang <fangyi...@huawei.com>
---
target/arm/cpu.c | 42 ++++++++++++++++++++++++++++++++++++++++++
target/arm/cpu.h | 27 +++++++++++++++++++++++++++
2 files changed, 69 insertions(+)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 056319859f..f1bac7452c 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -27,6 +27,7 @@
#include "qapi/visitor.h"
#include "cpu.h"
#include "internals.h"
+#include "qemu/units.h"
#include "exec/exec-all.h"
#include "hw/qdev-properties.h"
#if !defined(CONFIG_USER_ONLY)
@@ -997,6 +998,45 @@ uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz)
return (Aff1 << ARM_AFF1_SHIFT) | Aff0;
}
+static CPUCaches default_cache_info = {
+ .l1d_cache = &(CPUCacheInfo) {
+ .type = DATA_CACHE,
+ .level = 1,
+ .size = 64 * KiB,
+ .line_size = 64,
+ .associativity = 4,
+ .sets = 256,
+ .attributes = 0x02,
+ },
Would it be possible to populate this structure from the
CLIDR/CCSIDR ID register values, rather than having to
specify the same thing in two places?
Sorry I missed this reply.
I had tried to fetch CLIDR/CCSID ID register values of host cpu
from KVM, however I did not get the value expected. May I made
some mistakes in KVM side.
Thanks for your guide, I'll try to populate them again.
thanks
-- PMM
.
Thanks.
Ying.