On 1/12/21 2:52 PM, 罗勇刚(Yonggang Luo) wrote: > > > On Tue, Jan 12, 2021 at 5:23 PM Cédric Le Goater <c...@kaod.org > <mailto:c...@kaod.org>> wrote: >> >> > QEMU 5.2.x, an e300 based machine ppc603 are impacted. >> > Here is my fix, narrowed down to MSR_TGPR and MSR_ILE >> > ``` >> > From 42ce41671f1e6c4dd44e6fb481bbda9df09320bd Mon Sep 17 00:00:00 2001 >> > From: Yonggang Luo <luoyongg...@gmail.com <mailto:luoyongg...@gmail.com> >> > <mailto:luoyongg...@gmail.com <mailto:luoyongg...@gmail.com>>> >> > Date: Sun, 10 Jan 2021 00:08:00 -0800 >> > Subject: [PATCH] ppc: Fix rfi/rfid/hrfi/... emulation again >> > >> > This revert part mask bits for ppc603/ppc4x that disabled in >> > a2e71b28e832346409efc795ecd1f0a2bcb705a3. >> > Remove redundant macro MSR_BOOK3S_MASK. >> > Fixes boot VxWorks on e300 >> > >> > Signed-off-by: Yonggang Luo <luoyongg...@gmail.com >> > <mailto:luoyongg...@gmail.com> <mailto:luoyongg...@gmail.com >> > <mailto:luoyongg...@gmail.com>>> >> > --- >> > target/ppc/excp_helper.c | 5 +++-- >> > 1 file changed, 3 insertions(+), 2 deletions(-) >> > >> > diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c >> > index 1c48b9fdf6..df70c5a4e8 100644 >> > --- a/target/ppc/excp_helper.c >> > +++ b/target/ppc/excp_helper.c >> > @@ -1156,8 +1156,10 @@ static inline void do_rfi(CPUPPCState *env, >> > target_ulong nip, target_ulong msr) >> > { >> > CPUState *cs = env_cpu(env); >> > >> > - /* MSR:POW cannot be set by any form of rfi */ >> > + /* MSR:POW,TGPR,ILE cannot be set by any form of rfi */ >> > msr &= ~(1ULL << MSR_POW); >> > + msr &= ~(1ULL << MSR_TGPR); >> >> Indeed. The e300 user manual says that TGPR is cleared by rfi. We should >> add a per-cpu family mask and not a global setting. > Refer to https://www.nxp.com/docs/en/reference-manual/e300coreRM.pdf > <https://www.nxp.com/docs/en/reference-manual/e300coreRM.pdf> > > `Table 2-4. MSR Bit Settings` > > ``` > Temporary GPR remapping (implementation-specific) 0 Normal operation 1 TGPR > mode. GPR0–GPR3 are remapped to TGPR0–TGPR3 for use by TLB miss routines. The > contents of GPR0–GPR3 remain unchanged while MSR[TGPR] = 1. Attempts to use > GPR4–GPR31 with MSR[TGPR] = 1 yield undefined results. Temporarily replaces > TGPR0–TGPR3 with GPR0–GPR3 for use by TLB miss routines. The TGPR bit is set > when either an instruction TLB miss, data read miss, or data write miss > interrupt is taken. The TGPR bit is cleared by an rfi instruction. > ``` > >> >> > + msr &= ~(1ULL << MSR_ILE); >> >> that's curious. I am still trying to understand that part. May be this is >> due to the lack of HID2 modeling which contains a "True little-endian" bit. > > Don't understand this part, I am running VxWorks 6.9 on MPC8349EA > https://www.nxp.com/docs/en/reference-manual/MPC8349EARM.pdf > <https://www.nxp.com/docs/en/reference-manual/MPC8349EARM.pdf> > > Didn't got any idea about why MSR_ILE are set > >> >> Is your image Little endian ? >> > Big Endian vxworks image.
Can you share the image ? and the QEMU command line ? Thanks, C.
