Resending the MIPS pull request from MIPS patches from last week (2021-01-07) now than the "decodetree: Open files with encoding='utf-8'" patch got merged (commit 4cacecaaa2b).
Pre-existing checkpatch warnings in patch 23 (target/mips: Move common helpers from helper.c to cpu.c): ERROR: space prohibited after that '&' (ctx:WxW) #52: FILE: target/mips/cpu.c:53: + cu = (v >> CP0St_CU0) & 0xf; ^ ERROR: space prohibited after that '&' (ctx:WxW) #53: FILE: target/mips/cpu.c:54: + mx = (v >> CP0St_MX) & 0x1; ^ ERROR: space prohibited after that '&' (ctx:WxW) #54: FILE: target/mips/cpu.c:55: + ksu = (v >> CP0St_KSU) & 0x3; ^ ERROR: space prohibited after that '&' (ctx:WxW) #81: FILE: target/mips/cpu.c:82: + uint32_t ksux = (1 << CP0St_KX) & val; ^ ERROR: space prohibited after that '&' (ctx:WxW) #89: FILE: target/mips/cpu.c:90: + mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val); ^ ERROR: space prohibited after that '&' (ctx:WxW) #116: FILE: target/mips/cpu.c:117: + mask &= ~((1 << CP0Ca_WP) & val); ^ ERROR: space prohibited after that '&' (ctx:WxW) #121: FILE: target/mips/cpu.c:122: + if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) { ^ ERROR: space prohibited after that '&' (ctx:WxW) #131: FILE: target/mips/cpu.c:132: + if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) { ^ total: 8 errors, 0 warnings, 433 lines checked The following changes since commit 7c79721606be11b5bc556449e5bcbc331ef6867d: Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210113' into staging (2021-01-14 09:54:29 +0000) are available in the Git repository at: https://gitlab.com/philmd/qemu.git tags/mips-20210114 for you to fetch changes up to cd669e20516fad3d8154629f67d4b6caede9b381: docs/system: Remove deprecated 'fulong2e' machine alias (2021-01-14 17:13:54 +0100) ---------------------------------------------------------------- MIPS patches queue - Simplify CPU/ISA definitions - Various maintenance code movements in translate.c - Convert part of the MSA ASE instructions to decodetree - Convert some instructions removed from Release 6 to decodetree - Remove deprecated 'fulong2e' machine alias ---------------------------------------------------------------- Jiaxun Yang (1): target/mips/addr: Add translation helpers for KSEG1 Philippe Mathieu-Daudé (68): target/mips: Add CP0 Config0 register definitions for MIPS3 ISA target/mips: Replace CP0_Config0 magic values by proper definitions target/mips/mips-defs: Remove USE_HOST_FLOAT_REGS comment target/mips/mips-defs: Reorder CPU_MIPS5 definition target/mips/mips-defs: Rename CPU_MIPSxx Release 1 as CPU_MIPSxxR1 target/mips/mips-defs: Introduce CPU_MIPS64 and cpu_type_is_64bit() hw/mips/boston: Check 64-bit support with cpu_type_is_64bit() target/mips/mips-defs: Use ISA_MIPS32 definition to check Release 1 target/mips/mips-defs: Use ISA_MIPS32R2 definition to check Release 2 target/mips/mips-defs: Use ISA_MIPS32R3 definition to check Release 3 target/mips/mips-defs: Use ISA_MIPS32R5 definition to check Release 5 target/mips/mips-defs: Use ISA_MIPS32R6 definition to check Release 6 target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1 target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2 target/mips/mips-defs: Rename ISA_MIPS32R3 as ISA_MIPS_R3 target/mips/mips-defs: Rename ISA_MIPS32R5 as ISA_MIPS_R5 target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6 target/mips: Inline cpu_state_reset() in mips_cpu_reset() target/mips: Extract FPU helpers to 'fpu_helper.h' target/mips: Add !CONFIG_USER_ONLY comment after #endif target/mips: Remove consecutive CONFIG_USER_ONLY ifdefs target/mips: Move common helpers from helper.c to cpu.c target/mips: Rename helper.c as tlb_helper.c target/mips: Fix code style for checkpatch.pl target/mips: Move mmu_init() functions to tlb_helper.c target/mips: Rename translate_init.c as cpu-defs.c target/mips/translate: Extract DisasContext structure target/mips/translate: Add declarations for generic code target/mips: Replace gen_exception_err(err=0) by gen_exception_end() target/mips: Replace gen_exception_end(EXCP_RI) by gen_rsvd_instruction target/mips: Declare generic FPU / Coprocessor functions in translate.h target/mips: Extract FPU specific definitions to translate.h target/mips: Only build TCG code when CONFIG_TCG is set target/mips/translate: Extract decode_opc_legacy() from decode_opc() target/mips/translate: Expose check_mips_64() to 32-bit mode target/mips: Introduce ase_msa_available() helper target/mips: Simplify msa_reset() target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA target/mips: Simplify MSA TCG logic target/mips: Remove now unused ASE_MSA definition target/mips: Alias MSA vector registers on FPU scalar registers target/mips: Extract msa_translate_init() from mips_tcg_init() target/mips: Remove CPUMIPSState* argument from gen_msa*() methods target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ() target/mips: Move msa_reset() to msa_helper.c target/mips: Extract MSA helpers from op_helper.c target/mips: Extract MSA helper definitions target/mips: Declare gen_msa/_branch() in 'translate.h' target/mips: Extract MSA translation routines target/mips: Pass TCGCond argument to MSA gen_check_zero_element() target/mips: Introduce decode tree bindings for MSA ASE target/mips: Use decode_ase_msa() generated from decodetree target/mips: Extract LSA/DLSA translation generators target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes target/mips: Introduce decodetree helpers for Release6 LSA/DLSA opcodes target/mips: Remove now unreachable LSA/DLSA opcodes code target/mips: Convert Rel6 Special2 opcode to decodetree target/mips: Convert Rel6 COP1X opcode to decodetree target/mips: Convert Rel6 CACHE/PREF opcodes to decodetree target/mips: Convert Rel6 LWL/LWR/SWL/SWR opcodes to decodetree target/mips: Convert Rel6 LWLE/LWRE/SWLE/SWRE opcodes to decodetree target/mips: Convert Rel6 LDL/LDR/SDL/SDR opcodes to decodetree target/mips: Convert Rel6 LLD/SCD opcodes to decodetree target/mips: Convert Rel6 LL/SC opcodes to decodetree target/mips: Remove CPU_R5900 definition target/mips: Remove CPU_NANOMIPS32 definition target/mips: Remove vendor specific CPU definitions docs/system: Remove deprecated 'fulong2e' machine alias docs/system/deprecated.rst | 5 - docs/system/removed-features.rst | 5 + target/mips/cpu.h | 23 +- target/mips/fpu_helper.h | 59 + target/mips/helper.h | 436 +- target/mips/internal.h | 64 +- target/mips/mips-defs.h | 56 +- target/mips/translate.h | 177 + target/mips/msa_helper.h.inc | 443 ++ target/mips/mips32r6.decode | 36 + target/mips/mips64r6.decode | 27 + target/mips/msa32.decode | 29 + target/mips/msa64.decode | 17 + hw/mips/boston.c | 6 +- hw/mips/fuloong2e.c | 1 - linux-user/mips/cpu_loop.c | 7 +- target/mips/addr.c | 10 + target/mips/cp0_helper.c | 18 +- target/mips/cp0_timer.c | 4 +- target/mips/cpu.c | 255 +- target/mips/fpu_helper.c | 5 +- target/mips/gdbstub.c | 1 + target/mips/kvm.c | 13 +- target/mips/machine.c | 1 + target/mips/msa_helper.c | 430 ++ target/mips/msa_translate.c | 2286 ++++++++++ target/mips/op_helper.c | 396 +- target/mips/rel6_translate.c | 44 + target/mips/{helper.c => tlb_helper.c} | 266 +- target/mips/translate.c | 3860 ++++------------- target/mips/translate_addr_const.c | 61 + .../{translate_init.c.inc => cpu-defs.c.inc} | 128 +- target/mips/meson.build | 21 +- 33 files changed, 4757 insertions(+), 4433 deletions(-) create mode 100644 target/mips/fpu_helper.h create mode 100644 target/mips/translate.h create mode 100644 target/mips/msa_helper.h.inc create mode 100644 target/mips/mips32r6.decode create mode 100644 target/mips/mips64r6.decode create mode 100644 target/mips/msa32.decode create mode 100644 target/mips/msa64.decode create mode 100644 target/mips/msa_translate.c create mode 100644 target/mips/rel6_translate.c rename target/mips/{helper.c => tlb_helper.c} (87%) create mode 100644 target/mips/translate_addr_const.c rename target/mips/{translate_init.c.inc => cpu-defs.c.inc} (92%) -- 2.26.2