On Jan 18 21:55, Minwoo Im wrote: > On 21-01-18 10:47:00, Klaus Jensen wrote: > > From: Klaus Jensen <k.jen...@samsung.com> > > > > The controller registers are initially zero. Remove the redundant > > zeroing. > > > > Signed-off-by: Klaus Jensen <k.jen...@samsung.com> > > --- > > hw/block/nvme.c | 35 ----------------------------------- > > 1 file changed, 35 deletions(-) > > > > diff --git a/hw/block/nvme.c b/hw/block/nvme.c > > index f3bea582b3c0..9ee9570bb65c 100644 > > --- a/hw/block/nvme.c > > +++ b/hw/block/nvme.c > > @@ -4179,43 +4179,8 @@ static void nvme_init_cmb(NvmeCtrl *n, PCIDevice > > *pci_dev) > > > > static void nvme_init_pmr(NvmeCtrl *n, PCIDevice *pci_dev) > > { > > - /* PMR Capabities register */ > > - n->bar.pmrcap = 0; > > - NVME_PMRCAP_SET_RDS(n->bar.pmrcap, 0); > > - NVME_PMRCAP_SET_WDS(n->bar.pmrcap, 0); > > NVME_PMRCAP_SET_BIR(n->bar.pmrcap, NVME_PMR_BIR); > > - NVME_PMRCAP_SET_PMRTU(n->bar.pmrcap, 0); > > - /* Turn on bit 1 support */ > > This comment says that PMRWBM [1]th bit is set to PMRCAP below :). >
Thanks!
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