From: Bin Meng <bin.m...@windriver.com> Per the "Physical Layer Specification Version 8.00" chapter 7.5.2, "Data Read", there is a minimum 8 clock cycles (Nac) after the card response and before data block shows up on the data out line. This applies to both single and multiple block read operations.
Current implementation of single block read already satisfies the timing requirement as in the RESPONSE state after all responses are transferred the state remains unchanged. In the next 8 clock cycles it jumps to DATA_START state if data is ready. However we need an explicit state when expanding our support to multiple block read in the future. Let's add a new state PREP_DATA explicitly in the ssi-sd state machine to represent Nac. Note we don't change the single block read state machine to let it jump from RESPONSE state to DATA_START state as that effectively generates a 16 clock cycles Nac, which might not be safe. As the spec says the maximum Nac shall be calculated from several fields encoded in the CSD register, we don't want to bother updating CSD to ensure our Nac is within range to complicate things. Signed-off-by: Bin Meng <bin.m...@windriver.com> --- Changes in v2: - new patch: add a state representing Nac hw/sd/ssi-sd.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/hw/sd/ssi-sd.c b/hw/sd/ssi-sd.c index 8bccedfab2..5763afeba0 100644 --- a/hw/sd/ssi-sd.c +++ b/hw/sd/ssi-sd.c @@ -39,6 +39,7 @@ typedef enum { SSI_SD_CMDARG, SSI_SD_PREP_RESP, SSI_SD_RESPONSE, + SSI_SD_PREP_DATA, SSI_SD_DATA_START, SSI_SD_DATA_READ, SSI_SD_DATA_CRC16, @@ -194,6 +195,10 @@ static uint32_t ssi_sd_transfer(SSIPeripheral *dev, uint32_t val) s->mode = SSI_SD_CMD; } return 0xff; + case SSI_SD_PREP_DATA: + DPRINTF("Prepare data block (Nac)\n"); + s->mode = SSI_SD_DATA_START; + return 0xff; case SSI_SD_DATA_START: DPRINTF("Start read block\n"); s->mode = SSI_SD_DATA_READ; -- 2.25.1