On Mon, 1 Feb 2021 16:59:31 -0800 Ben Widawsky <ben.widaw...@intel.com> wrote:
> This cleanup will make it easier to add support for CXL to the mix. > > Signed-off-by: Ben Widawsky <ben.widaw...@intel.com> One trivial but up to you on whether you think it's worth changing. > --- > hw/i386/acpi-build.c | 31 +++++++++++++++++-------------- > 1 file changed, 17 insertions(+), 14 deletions(-) > > diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c > index f56d699c7f..cf6eb54c22 100644 > --- a/hw/i386/acpi-build.c > +++ b/hw/i386/acpi-build.c > @@ -1194,6 +1194,20 @@ static void build_smb0(Aml *table, I2CBus *smbus, int > devnr, int func) > aml_append(table, scope); > } > > +enum { PCI, PCIE }; > +static void init_pci_acpi(Aml *dev, int uid, int type) > +{ > + if (type == PCI) { > + aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); > + aml_append(dev, aml_name_decl("_UID", aml_int(uid))); > + } else { > + aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); > + aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); > + aml_append(dev, aml_name_decl("_UID", aml_int(uid))); > + aml_append(dev, build_q35_osc_method()); > + } Gut feeling would be this will end up nicer as a switch. I suspect this isn't the last time this will get extended! > +} > + > static void > build_dsdt(GArray *table_data, BIOSLinker *linker, > AcpiPmInfo *pm, AcpiMiscInfo *misc, > @@ -1222,9 +1236,8 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, > if (misc->is_piix4) { > sb_scope = aml_scope("_SB"); > dev = aml_device("PCI0"); > - aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); > + init_pci_acpi(dev, 0, PCI); > aml_append(dev, aml_name_decl("_ADR", aml_int(0))); > - aml_append(dev, aml_name_decl("_UID", aml_int(0))); > aml_append(sb_scope, dev); > aml_append(dsdt, sb_scope); > > @@ -1238,11 +1251,8 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, > } else { > sb_scope = aml_scope("_SB"); > dev = aml_device("PCI0"); > - aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); > - aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); > + init_pci_acpi(dev, 0, PCIE); > aml_append(dev, aml_name_decl("_ADR", aml_int(0))); > - aml_append(dev, aml_name_decl("_UID", aml_int(0))); > - aml_append(dev, build_q35_osc_method()); > aml_append(sb_scope, dev); > > if (pm->smi_on_cpuhp) { > @@ -1345,15 +1355,8 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, > > scope = aml_scope("\\_SB"); > dev = aml_device("PC%.02X", bus_num); > - aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); > aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); > - if (pci_bus_is_express(bus)) { > - aml_append(dev, aml_name_decl("_HID", > aml_eisaid("PNP0A08"))); > - aml_append(dev, aml_name_decl("_CID", > aml_eisaid("PNP0A03"))); > - aml_append(dev, build_q35_osc_method()); > - } else { > - aml_append(dev, aml_name_decl("_HID", > aml_eisaid("PNP0A03"))); > - } > + init_pci_acpi(dev, bus_num, pci_bus_is_express(bus) ? PCIE : > PCI); > > if (numa_node != NUMA_NODE_UNASSIGNED) { > aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node)));