From: Vincent Palatin <vpala...@chromium.org>
eMMC CSD is similar to SD with an option to refer EXT_CSD for larger
devices.
Signed-off-by: Sai Pavan Boddu <sai.pavan.bo...@xilinx.com>
---
hw/sd/sd.c | 57 +++++++++++++++++++++++++++++++++++++++++++++++++++++++--
1 file changed, 55 insertions(+), 2 deletions(-)
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
index 430bea5..4c211ba 100644
--- a/hw/sd/sd.c
+++ b/hw/sd/sd.c
@@ -135,6 +135,7 @@ struct SDState {
uint64_t data_start;
uint32_t data_offset;
uint8_t data[512];
+ uint8_t ext_csd[512];
qemu_irq readonly_cb;
qemu_irq inserted_cb;
QEMUTimer *ocr_power_timer;
@@ -389,6 +390,51 @@ static const uint8_t sd_csd_rw_mask[16] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xfe,
};
+static void mmc_set_ext_csd(SDState *sd, uint64_t size)
+{
+ uint32_t sectcount = size >> HWBLOCK_SHIFT;
+
+ memset(sd->ext_csd, 0, sizeof(sd->ext_csd));
+ sd->ext_csd[504] = 0x1; /* supported command sets */
+ sd->ext_csd[503] = 0x1; /* HPI features */
+ sd->ext_csd[502] = 0x1; /* Background operations support */
+ sd->ext_csd[241] = 0xA; /* 1st initialization time after partitioning */
+ sd->ext_csd[232] = 0x1; /* Trim multiplier */
+ sd->ext_csd[231] = 0x15; /* Secure feature support */
+ sd->ext_csd[230] = 0x96; /* Secure erase support */
+ sd->ext_csd[229] = 0x96; /* Secure TRIM multiplier */
+ sd->ext_csd[228] = 0x7; /* Boot information */
+ sd->ext_csd[226] = 0x8; /* Boot partition size */
+ sd->ext_csd[225] = 0x6; /* Access size */
+ sd->ext_csd[224] = 0x4; /* HC Erase unit size */
+ sd->ext_csd[223] = 0x1; /* HC erase timeout */
+ sd->ext_csd[222] = 0x1; /* Reliable write sector count */
+ sd->ext_csd[221] = 0x4; /* HC write protect group size */
+ sd->ext_csd[220] = 0x8; /* Sleep current VCC */
+ sd->ext_csd[219] = 0x7; /* Sleep current VCCQ */
+ sd->ext_csd[217] = 0x11; /* Sleep/Awake timeout */
+ sd->ext_csd[215] = (sectcount >> 24) & 0xff; /* Sector count */
+ sd->ext_csd[214] = (sectcount >> 16) & 0xff; /* ... */
+ sd->ext_csd[213] = (sectcount >> 8) & 0xff; /* ... */
+ sd->ext_csd[212] = (sectcount & 0xff); /* ... */
+ sd->ext_csd[210] = 0xa; /* Min write perf for 8bit@52Mhz */
+ sd->ext_csd[209] = 0xa; /* Min read perf for 8bit@52Mhz */
+ sd->ext_csd[208] = 0xa; /* Min write perf for 4bit@52Mhz */
+ sd->ext_csd[207] = 0xa; /* Min read perf for 4bit@52Mhz */
+ sd->ext_csd[206] = 0xa; /* Min write perf for 4bit@26Mhz */
+ sd->ext_csd[205] = 0xa; /* Min read perf for 4bit@26Mhz */
+ sd->ext_csd[199] = 0x1; /* Partition switching timing */
+ sd->ext_csd[198] = 0x1; /* Out-of-interrupt busy timing */
+ sd->ext_csd[196] = 0xFF; /* Card type */
+ sd->ext_csd[194] = 0x2; /* CSD Structure version */
+ sd->ext_csd[192] = 0x5; /* Extended CSD revision */
+ sd->ext_csd[168] = 0x1; /* RPMB size */
+ sd->ext_csd[160] = 0x3; /* Partinioning support */
+ sd->ext_csd[159] = 0x00; /* Max enhanced area size */
+ sd->ext_csd[158] = 0x00; /* ... */
+ sd->ext_csd[157] = 0xEC; /* ... */
+}
+
static void sd_set_csd(SDState *sd, uint64_t size)
{
int hwblock_shift = HWBLOCK_SHIFT;
@@ -402,8 +448,11 @@ static void sd_set_csd(SDState *sd, uint64_t size)
}
csize = (size >> (CMULT_SHIFT + hwblock_shift)) - 1;
- if (size <= SDSC_MAX_CAPACITY) { /* Standard Capacity SD */
- sd->csd[0] = 0x00; /* CSD structure */
+ if (size <= SDSC_MAX_CAPACITY || sd->emmc) { /* Standard Capacity SD */
+ if (sd->emmc && size >= SDSC_MAX_CAPACITY) {
+ csize = 0xfff;
+ }
+ sd->csd[0] = sd->emmc ? 0xd0 : 0x00; /* CSD structure */
sd->csd[1] = 0x26; /* Data read access-time-1 */
sd->csd[2] = 0x00; /* Data read access-time-2 */
sd->csd[3] = 0x32; /* Max. data transfer rate: 25 MHz */
@@ -447,6 +496,10 @@ static void sd_set_csd(SDState *sd, uint64_t size)
sd->csd[14] = 0x00;
}
sd->csd[15] = (sd_crc7(sd->csd, 15) << 1) | 1;
+
+ if (sd->emmc) {
+ mmc_set_ext_csd(sd, size);
+ }
}
static void sd_set_rca(SDState *sd, uint16_t value)
--
2.7.4
