Alistair Francis (5): target/riscv: Convert the RISC-V exceptions to an enum target/riscv: Use the RiscVException enum for CSR predicates target/riscv: Fix 32-bit HS mode access permissions target/riscv: Use the RiscVException enum for CSR operations target/riscv: Use RiscVException enum for CSR access
target/riscv/cpu.h | 28 +- target/riscv/cpu_bits.h | 44 +-- target/riscv/cpu.c | 2 +- target/riscv/cpu_helper.c | 4 +- target/riscv/csr.c | 753 ++++++++++++++++++++++---------------- target/riscv/gdbstub.c | 8 +- target/riscv/op_helper.c | 18 +- 7 files changed, 499 insertions(+), 358 deletions(-) -- 2.30.1
