The following changes since commit c95bd5ff1660883d15ad6e0005e4c8571604f51a:
Merge remote-tracking branch 'remotes/philmd/tags/mips-fixes-20210322' into
staging (2021-03-22 14:26:13 +0000)
are available in the Git repository at:
g...@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210322-2
for you to fetch changes up to 9a27f69bd668d9d71674407badc412ce1231c7d5:
target/riscv: Prevent lost illegal instruction exceptions (2021-03-22
21:54:40 -0400)
----------------------------------------------------------------
RISC-V PR for 6.0
This PR includes:
- Fix for vector CSR access
- Improvements to the Ibex UART device
- PMP improvements and bug fixes
- Hypervisor extension bug fixes
- ramfb support for the virt machine
- Fast read support for SST flash
- Improvements to the microchip_pfsoc machine
----------------------------------------------------------------
Alexander Wagner (1):
hw/char: disable ibex uart receive if the buffer is full
Asherah Connor (2):
hw/riscv: Add fw_cfg support to virt
hw/riscv: allow ramfb on virt
Bin Meng (3):
hw/block: m25p80: Support fast read for SST flashes
hw/riscv: microchip_pfsoc: Map EMMC/SD mux register
docs/system: riscv: Add documentation for 'microchip-icicle-kit' machine
Frank Chang (1):
target/riscv: fix vs() to return proper error code
Georg Kotheimer (6):
target/riscv: Adjust privilege level for HLV(X)/HSV instructions
target/riscv: Make VSTIP and VSEIP read-only in hip
target/riscv: Use background registers also for MSTATUS_MPV
target/riscv: Fix read and write accesses to vsip and vsie
target/riscv: Add proper two-stage lookup exception detection
target/riscv: Prevent lost illegal instruction exceptions
Jim Shu (3):
target/riscv: propagate PMP permission to TLB page
target/riscv: add log of PMP permission checking
target/riscv: flush TLB pages if PMP permission has been changed
docs/system/riscv/microchip-icicle-kit.rst | 89 ++++++++++++++
docs/system/target-riscv.rst | 1 +
include/hw/char/ibex_uart.h | 4 +
include/hw/riscv/microchip_pfsoc.h | 1 +
include/hw/riscv/virt.h | 2 +
target/riscv/cpu.h | 4 +
target/riscv/pmp.h | 4 +-
hw/block/m25p80.c | 3 +
hw/char/ibex_uart.c | 23 +++-
hw/riscv/microchip_pfsoc.c | 6 +
hw/riscv/virt.c | 33 ++++++
target/riscv/cpu.c | 1 +
target/riscv/cpu_helper.c | 144 +++++++++++++++--------
target/riscv/csr.c | 77 +++++++------
target/riscv/pmp.c | 84 ++++++++++----
target/riscv/translate.c | 179 +----------------------------
hw/riscv/Kconfig | 1 +
17 files changed, 367 insertions(+), 289 deletions(-)
create mode 100644 docs/system/riscv/microchip-icicle-kit.rst
