we need this for KVM too.
Signed-off-by: Claudio Fontana <cfont...@suse.de>
---
target/arm/cpu-sysemu.c | 60 ++++++++++++++++++++++++++++++++++++++++
target/arm/cpu-user.c | 5 ++++
target/arm/tcg/helper.c | 61 -----------------------------------------
3 files changed, 65 insertions(+), 61 deletions(-)
diff --git a/target/arm/cpu-sysemu.c b/target/arm/cpu-sysemu.c
index d510382742..5265de1c87 100644
--- a/target/arm/cpu-sysemu.c
+++ b/target/arm/cpu-sysemu.c
@@ -350,3 +350,63 @@ void aarch64_sync_64_to_32(CPUARMState *env)
env->regs[15] = env->pc;
}
+
+/*
+ * Return the exception level to which exceptions should be taken
+ * via SVEAccessTrap. If an exception should be routed through
+ * AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should
+ * take care of raising that exception.
+ * C.f. the ARM pseudocode function CheckSVEEnabled.
+ */
+int sve_exception_el(CPUARMState *env, int el)
+{
+ uint64_t hcr_el2 = arm_hcr_el2_eff(env);
+
+ if (el <= 1 && (hcr_el2 & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
+ bool disabled = false;
+
+ /* The CPACR.ZEN controls traps to EL1:
+ * 0, 2 : trap EL0 and EL1 accesses
+ * 1 : trap only EL0 accesses
+ * 3 : trap no accesses
+ */
+ if (!extract32(env->cp15.cpacr_el1, 16, 1)) {
+ disabled = true;
+ } else if (!extract32(env->cp15.cpacr_el1, 17, 1)) {
+ disabled = el == 0;
+ }
+ if (disabled) {
+ /* route_to_el2 */
+ return hcr_el2 & HCR_TGE ? 2 : 1;
+ }
+
+ /* Check CPACR.FPEN. */
+ if (!extract32(env->cp15.cpacr_el1, 20, 1)) {
+ disabled = true;
+ } else if (!extract32(env->cp15.cpacr_el1, 21, 1)) {
+ disabled = el == 0;
+ }
+ if (disabled) {
+ return 0;
+ }
+ }
+
+ /* CPTR_EL2. Since TZ and TFP are positive,
+ * they will be zero when EL2 is not present.
+ */
+ if (el <= 2 && arm_is_el2_enabled(env)) {
+ if (env->cp15.cptr_el[2] & CPTR_TZ) {
+ return 2;
+ }
+ if (env->cp15.cptr_el[2] & CPTR_TFP) {
+ return 0;
+ }
+ }
+
+ /* CPTR_EL3. Since EZ is negative we must check for EL3. */
+ if (arm_feature(env, ARM_FEATURE_EL3)
+ && !(env->cp15.cptr_el[3] & CPTR_EZ)) {
+ return 3;
+ }
+ return 0;
+}
diff --git a/target/arm/cpu-user.c b/target/arm/cpu-user.c
index 0225089e46..39093ade76 100644
--- a/target/arm/cpu-user.c
+++ b/target/arm/cpu-user.c
@@ -33,3 +33,8 @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t
excp_idx,
{
return 1;
}
+
+int sve_exception_el(CPUARMState *env, int el)
+{
+ return 0;
+}
diff --git a/target/arm/tcg/helper.c b/target/arm/tcg/helper.c
index 03dee5b447..988ee1c49c 100644
--- a/target/arm/tcg/helper.c
+++ b/target/arm/tcg/helper.c
@@ -329,67 +329,6 @@ uint64_t arm_hcr_el2_eff(CPUARMState *env)
return ret;
}
-/* Return the exception level to which exceptions should be taken
- * via SVEAccessTrap. If an exception should be routed through
- * AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should
- * take care of raising that exception.
- * C.f. the ARM pseudocode function CheckSVEEnabled.
- */
-int sve_exception_el(CPUARMState *env, int el)
-{
-#ifndef CONFIG_USER_ONLY
- uint64_t hcr_el2 = arm_hcr_el2_eff(env);
-
- if (el <= 1 && (hcr_el2 & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
- bool disabled = false;
-
- /* The CPACR.ZEN controls traps to EL1:
- * 0, 2 : trap EL0 and EL1 accesses
- * 1 : trap only EL0 accesses
- * 3 : trap no accesses
- */
- if (!extract32(env->cp15.cpacr_el1, 16, 1)) {
- disabled = true;
- } else if (!extract32(env->cp15.cpacr_el1, 17, 1)) {
- disabled = el == 0;
- }
- if (disabled) {
- /* route_to_el2 */
- return hcr_el2 & HCR_TGE ? 2 : 1;
- }
-
- /* Check CPACR.FPEN. */
- if (!extract32(env->cp15.cpacr_el1, 20, 1)) {
- disabled = true;
- } else if (!extract32(env->cp15.cpacr_el1, 21, 1)) {
- disabled = el == 0;
- }
- if (disabled) {
- return 0;
- }
- }
-
- /* CPTR_EL2. Since TZ and TFP are positive,
- * they will be zero when EL2 is not present.
- */
- if (el <= 2 && arm_is_el2_enabled(env)) {
- if (env->cp15.cptr_el[2] & CPTR_TZ) {
- return 2;
- }
- if (env->cp15.cptr_el[2] & CPTR_TFP) {
- return 0;
- }
- }
-
- /* CPTR_EL3. Since EZ is negative we must check for EL3. */
- if (arm_feature(env, ARM_FEATURE_EL3)
- && !(env->cp15.cptr_el[3] & CPTR_EZ)) {
- return 3;
- }
-#endif
- return 0;
-}
-
void hw_watchpoint_update(ARMCPU *cpu, int n)
{
CPUARMState *env = &cpu->env;
--
2.26.2
