restrict zcr_el1, zcr_el2, zcr_no_el2, zcr_el3 reginfo,
and the related SVE functions to TARGET_AARCH64.
Signed-off-by: Claudio Fontana <cfont...@suse.de>
---
target/arm/tcg/cpregs.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/target/arm/tcg/cpregs.c b/target/arm/tcg/cpregs.c
index a72c9378b2..d72832aeaa 100644
--- a/target/arm/tcg/cpregs.c
+++ b/target/arm/tcg/cpregs.c
@@ -5792,6 +5792,8 @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
REGINFO_SENTINEL
};
+#ifdef TARGET_AARCH64
+
static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
@@ -5844,6 +5846,8 @@ static const ARMCPRegInfo zcr_el3_reginfo = {
.writefn = zcr_write, .raw_writefn = raw_write
};
+#endif /* TARGET_AARCH64 */
+
static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
@@ -7573,6 +7577,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
define_arm_cp_regs(cpu, vhe_reginfo);
}
+#ifdef TARGET_AARCH64
if (cpu_isar_feature(aa64_sve, cpu)) {
define_one_arm_cp_reg(cpu, &zcr_el1_reginfo);
if (arm_feature(env, ARM_FEATURE_EL2)) {
@@ -7585,7 +7590,6 @@ void register_cp_regs_for_features(ARMCPU *cpu)
}
}
-#ifdef TARGET_AARCH64
if (cpu_isar_feature(aa64_pauth, cpu)) {
define_arm_cp_regs(cpu, pauth_reginfo);
}
@@ -7615,7 +7619,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
define_arm_cp_regs(cpu, mte_tco_ro_reginfo);
define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo);
}
-#endif
+#endif /* TARGET_AARCH64 */
if (cpu_isar_feature(any_predinv, cpu)) {
define_arm_cp_regs(cpu, predinv_reginfo);
--
2.26.2
