[PATCH 3/3] pcie_root_port: reorder procedures in realize()

[Tom Yan]

There are a bunch of pcie_cap_*_init() in the realize method of the
pcie root port devices that do not have return value. They can probably
be called after the slot is successfully added to an created chassis
(i.e. the slot number to use is final).
of them makes use of the slot number.

Signed-off-by: Tom Yan <tom.t...@gmail.com>
---
 hw/pci-bridge/pcie_root_port.c     | 10 +++++-----
 hw/pci-bridge/xio3130_downstream.c |  9 +++++----
 2 files changed, 10 insertions(+), 9 deletions(-)

diff --git a/hw/pci-bridge/pcie_root_port.c b/hw/pci-bridge/pcie_root_port.c
index f1cfe9d14a..2bd2d02ccb 100644
--- a/hw/pci-bridge/pcie_root_port.c
+++ b/hw/pci-bridge/pcie_root_port.c
@@ -92,11 +92,6 @@ static void rp_realize(PCIDevice *d, Error **errp)
         goto err_int;
     }
 
-    pcie_cap_arifwd_init(d);
-    pcie_cap_deverr_init(d);
-    pcie_cap_slot_init(d, s);
-    pcie_cap_root_init(d);
-
     pcie_chassis_create(s->chassis);
     rc = pcie_chassis_add_slot(s);
     if (rc < 0) {
@@ -104,6 +99,11 @@ static void rp_realize(PCIDevice *d, Error **errp)
         goto err_pcie_cap;
     }
 
+    pcie_cap_arifwd_init(d);
+    pcie_cap_deverr_init(d);
+    pcie_cap_slot_init(d, s);
+    pcie_cap_root_init(d);
+
     rc = pcie_aer_init(d, PCI_ERR_VER, rpc->aer_offset,
                        PCI_ERR_SIZEOF, errp);
     if (rc < 0) {
diff --git a/hw/pci-bridge/xio3130_downstream.c 
b/hw/pci-bridge/xio3130_downstream.c
index 04aae72cd6..b7a92693ee 100644
--- a/hw/pci-bridge/xio3130_downstream.c
+++ b/hw/pci-bridge/xio3130_downstream.c
@@ -92,10 +92,6 @@ static void xio3130_downstream_realize(PCIDevice *d, Error 
**errp)
     if (rc < 0) {
         goto err_msi;
     }
-    pcie_cap_flr_init(d);
-    pcie_cap_deverr_init(d);
-    pcie_cap_slot_init(d, s);
-    pcie_cap_arifwd_init(d);
 
     pcie_chassis_create(s->chassis);
     rc = pcie_chassis_add_slot(s);
@@ -104,6 +100,11 @@ static void xio3130_downstream_realize(PCIDevice *d, Error 
**errp)
         goto err_pcie_cap;
     }
 
+    pcie_cap_flr_init(d);
+    pcie_cap_deverr_init(d);
+    pcie_cap_slot_init(d, s);
+    pcie_cap_arifwd_init(d);
+
     rc = pcie_aer_init(d, PCI_ERR_VER, XIO3130_AER_OFFSET,
                        PCI_ERR_SIZEOF, errp);
     if (rc < 0) {
-- 
2.31.1