On Fri, 2 Apr 2021 at 09:48, Zenghui Yu <yuzeng...@huawei.com> wrote:
>
> The GSIV values in SMMUv3 IORT node are not correct as they don't match
> the SMMUIrq enumeration, which describes the IRQ<->PIN mapping used by
> our emulated vSMMU.
>
> Fixes: a703b4f6c1ee ("hw/arm/virt-acpi-build: Add smmuv3 node in IORT table")
> Signed-off-by: Zenghui Yu <yuzeng...@huawei.com>
> ---
> hw/arm/virt-acpi-build.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
> index f5a2b2d4cb..60fe2e65a7 100644
> --- a/hw/arm/virt-acpi-build.c
> +++ b/hw/arm/virt-acpi-build.c
> @@ -292,8 +292,8 @@ build_iort(GArray *table_data, BIOSLinker *linker,
> VirtMachineState *vms)
> smmu->flags = cpu_to_le32(ACPI_IORT_SMMU_V3_COHACC_OVERRIDE);
> smmu->event_gsiv = cpu_to_le32(irq);
> smmu->pri_gsiv = cpu_to_le32(irq + 1);
> - smmu->gerr_gsiv = cpu_to_le32(irq + 2);
> - smmu->sync_gsiv = cpu_to_le32(irq + 3);
> + smmu->sync_gsiv = cpu_to_le32(irq + 2);
> + smmu->gerr_gsiv = cpu_to_le32(irq + 3);
>
> /* Identity RID mapping covering the whole input RID range */
> idmap = &smmu->id_mapping_array[0];
> --
Applied to target-arm.next, thanks.
-- PMM
