ping +1.
On 2021/2/12 下午11:02, LIU Zhiwei wrote:
This patchset implements the packed extension for RISC-V on QEMU.
This patchset have passed all my direct Linux user mode cases(RV64) and
bare metal cases(RV32) on X86-64 Ubuntu host machine. I will later push
these test cases to my repo(https://github.com/romanheros/qemu.git
branch:packed-upstream-v1).
I have ported packed extension on RISU, but I didn't find a simulator or
hardware to compare with. If anyone have one, please let me know.
Features:
* support specification packed extension
v0.9.2(https://github.com/riscv/riscv-p-spec/)
* support basic packed extension.
* support Zp64.
LIU Zhiwei (38):
target/riscv: implementation-defined constant parameters
target/riscv: Hoist vector functions
target/riscv: Fixup saturate subtract function
target/riscv: 16-bit Addition & Subtraction Instructions
target/riscv: 8-bit Addition & Subtraction Instruction
target/riscv: SIMD 16-bit Shift Instructions
target/riscv: SIMD 8-bit Shift Instructions
target/riscv: SIMD 16-bit Compare Instructions
target/riscv: SIMD 8-bit Compare Instructions
target/riscv: SIMD 16-bit Multiply Instructions
target/riscv: SIMD 8-bit Multiply Instructions
target/riscv: SIMD 16-bit Miscellaneous Instructions
target/riscv: SIMD 8-bit Miscellaneous Instructions
target/riscv: 8-bit Unpacking Instructions
target/riscv: 16-bit Packing Instructions
target/riscv: Signed MSW 32x32 Multiply and Add Instructions
target/riscv: Signed MSW 32x16 Multiply and Add Instructions
target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions
target/riscv: Signed 16-bit Multiply 64-bit Add/Subtract Instructions
target/riscv: Partial-SIMD Miscellaneous Instructions
target/riscv: 8-bit Multiply with 32-bit Add Instructions
target/riscv: 64-bit Add/Subtract Instructions
target/riscv: 32-bit Multiply 64-bit Add/Subtract Instructions
target/riscv: Signed 16-bit Multiply with 64-bit Add/Subtract
Instructions
target/riscv: Non-SIMD Q15 saturation ALU Instructions
target/riscv: Non-SIMD Q31 saturation ALU Instructions
target/riscv: 32-bit Computation Instructions
target/riscv: Non-SIMD Miscellaneous Instructions
target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions
target/riscv: RV64 Only SIMD 32-bit Shift Instructions
target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions
target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions
target/riscv: RV64 Only 32-bit Multiply Instructions
target/riscv: RV64 Only 32-bit Multiply & Add Instructions
target/riscv: RV64 Only 32-bit Parallel Multiply & Add Instructions
target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions
target/riscv: RV64 Only 32-bit Packing Instructions
target/riscv: configure and turn on packed extension from command line
target/riscv/cpu.c | 32 +
target/riscv/cpu.h | 6 +
target/riscv/helper.h | 332 ++
target/riscv/insn32-64.decode | 93 +-
target/riscv/insn32.decode | 285 ++
target/riscv/insn_trans/trans_rvp.c.inc | 1224 +++++++
target/riscv/internals.h | 50 +
target/riscv/meson.build | 1 +
target/riscv/packed_helper.c | 3862 +++++++++++++++++++++++
target/riscv/translate.c | 3 +
target/riscv/vector_helper.c | 90 +-
11 files changed, 5912 insertions(+), 66 deletions(-)
create mode 100644 target/riscv/insn_trans/trans_rvp.c.inc
create mode 100644 target/riscv/packed_helper.c