On 4/15/21 4:54 PM, Peter Maydell wrote:
> On Thu, 15 Apr 2021 at 15:32, Alex Bennée <alex.ben...@linaro.org> wrote:
>> --8<---------------cut here---------------start------------->8---
>> accel/tcg: avoid re-translating one-shot instructions
>>
>> By definition a single instruction is capable of being an IO
>> instruction. This avoids a problem of triggering a cpu_io_recompile on
>> a non-cached translation which would only do exactly this anyway.
>>
>> Signed-off-by: Alex Bennée <alex.ben...@linaro.org>
>>
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>> accel/tcg/translate-all.c | 2 +-
>>
>> modified accel/tcg/translate-all.c
>> @@ -1863,7 +1863,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
>>
>> if (phys_pc == -1) {
>> /* Generate a one-shot TB with 1 insn in it */
>> - cflags = (cflags & ~CF_COUNT_MASK) | 1;
>> + cflags = (cflags & ~CF_COUNT_MASK) | CF_LAST_IO | 1;
>> }
>>
>> max_insns = cflags & CF_COUNT_MASK;
>> --8<---------------cut here---------------end--------------->8---
>
> Yes, this fixes the problem. Do we want to put this in for 6.0? My
> feeling is that executing from non-RAM is pretty niche, so maybe
> if we need an rc4 anyway, but this isn't important enough to cause an
> rc4 itself.
Isn't it the default for Aspeed machines (with U-Boot)? (Cc'ing Cédric).
