Based-on: 20210416210240.1591291-1-richard.hender...@linaro.org
("[PATCH v5 for-6.1 00/81] target/arm: Implement SVE2")https://gitlab.com/rth7680/qemu/-/tree/tgt-arm-bf16 https://gitlab.com/rth7680/qemu/-/commit/2ecc372b672d11fdc4e2573d789bfb3f5e6cba48 Bfloat16 is a set of 2 tightly-coupled features adding to AArch32 NEON, AArch64 AdvSIMD, and AArch64 SVE1. That said, there are helper functions and decode patterns in the SVE2 patch set that help here, so I've based this patchset on that. Tested against FVP 11.13.36 via RISU. r~ Richard Henderson (11): target/arm: Add isar_feature_{aa32,aa64,aa64_sve}_bf16 target/arm: Unify unallocated path in disas_fp_1src target/arm: Implement scalar float32 to bfloat16 conversion target/arm: Implement vector float32 to bfloat16 conversion fpu: Add float_round_to_odd_inf target/arm: Implement bfloat16 dot product (vector) target/arm: Implement bfloat16 dot product (indexed) target/arm: Implement bfloat16 matrix multiply accumulate target/arm: Implement bfloat widening fma (vector) target/arm: Implement bfloat widening fma (indexed) target/arm: Enable BFloat16 extensions include/fpu/softfloat-types.h | 4 +- target/arm/cpu.h | 15 ++++ target/arm/helper-sve.h | 4 + target/arm/helper.h | 15 ++++ target/arm/neon-dp.decode | 1 + target/arm/neon-shared.decode | 11 +++ target/arm/sve.decode | 19 ++++- target/arm/vfp.decode | 2 + fpu/softfloat.c | 8 +- target/arm/cpu64.c | 3 + target/arm/cpu_tcg.c | 1 + target/arm/sve_helper.c | 2 + target/arm/translate-a64.c | 142 +++++++++++++++++++++++++++----- target/arm/translate-sve.c | 112 +++++++++++++++++++++++++ target/arm/vec_helper.c | 138 +++++++++++++++++++++++++++++++ target/arm/vfp_helper.c | 12 +++ target/arm/translate-neon.c.inc | 91 ++++++++++++++++++++ target/arm/translate-vfp.c.inc | 24 ++++++ 18 files changed, 580 insertions(+), 24 deletions(-) -- 2.25.1
