Re: [PATCH] target/mips: Fix CACHEE opcode (CACHE using EVA addressing)

[Philippe Mathieu-Daudé]

On 4/20/21 7:54 PM, Philippe Mathieu-Daudé wrote:
> The CACHEE opcode "requires CP0 privilege".
> 
> The pseudocode checks in the ISA manual is:
> 
>     if is_eva and not C0.Config5.EVA:
>       raise exception('RI')
> 
>     if not IsCoprocessor0Enabled():
>       raise coprocessor_exception(0)
> 
> Add the missing checks.
> 
> Inspired-by: Richard Henderson <richard.hender...@linaro.org>
> Signed-off-by: Philippe Mathieu-Daudé <f4...@amsat.org>
> ---
>  target/mips/translate.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)

Thanks, applied to mips-next.