Expand the single-use macros into the new functions. Use cpu_ldsb_mmuidx_ra and cpu_ldsw_le_mmuidx_ra so that the trace event receives the correct sign flag.
Signed-off-by: Richard Henderson <richard.hender...@linaro.org> --- tcg/tci.c | 215 +++++++++++++++++++----------------------------------- 1 file changed, 75 insertions(+), 140 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index ff096e1e32..a23f813305 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -286,34 +286,77 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, TCGCond condition) return result; } -#define qemu_ld_ub \ - cpu_ldub_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr) -#define qemu_ld_leuw \ - cpu_lduw_le_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr) -#define qemu_ld_leul \ - cpu_ldl_le_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr) -#define qemu_ld_leq \ - cpu_ldq_le_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr) -#define qemu_ld_beuw \ - cpu_lduw_be_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr) -#define qemu_ld_beul \ - cpu_ldl_be_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr) -#define qemu_ld_beq \ - cpu_ldq_be_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr) -#define qemu_st_b(X) \ - cpu_stb_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr) -#define qemu_st_lew(X) \ - cpu_stw_le_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr) -#define qemu_st_lel(X) \ - cpu_stl_le_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr) -#define qemu_st_leq(X) \ - cpu_stq_le_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr) -#define qemu_st_bew(X) \ - cpu_stw_be_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr) -#define qemu_st_bel(X) \ - cpu_stl_be_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr) -#define qemu_st_beq(X) \ - cpu_stq_be_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr) +static uint64_t tci_qemu_ld(CPUArchState *env, target_ulong taddr, + TCGMemOpIdx oi, const void *tb_ptr) +{ + uintptr_t ra = (uintptr_t)tb_ptr; + int mmu_idx = get_mmuidx(oi); + MemOp mop = get_memop(oi); + + switch (mop & (MO_BSWAP | MO_SSIZE)) { + case MO_UB: + return cpu_ldub_mmuidx_ra(env, taddr, mmu_idx, ra); + case MO_SB: + return cpu_ldsb_mmuidx_ra(env, taddr, mmu_idx, ra); + case MO_LEUW: + return cpu_lduw_le_mmuidx_ra(env, taddr, mmu_idx, ra); + case MO_BEUW: + return cpu_lduw_be_mmuidx_ra(env, taddr, mmu_idx, ra); + case MO_LESW: + return cpu_ldsw_le_mmuidx_ra(env, taddr, mmu_idx, ra); + case MO_BESW: + return cpu_ldsw_be_mmuidx_ra(env, taddr, mmu_idx, ra); + case MO_LEUL: + return cpu_ldl_le_mmuidx_ra(env, taddr, mmu_idx, ra); + case MO_BEUL: + return cpu_ldl_be_mmuidx_ra(env, taddr, mmu_idx, ra); + case MO_LESL: + return (int32_t)cpu_ldl_le_mmuidx_ra(env, taddr, mmu_idx, ra); + case MO_BESL: + return (int32_t)cpu_ldl_be_mmuidx_ra(env, taddr, mmu_idx, ra); + case MO_LEQ: + return cpu_ldq_le_mmuidx_ra(env, taddr, mmu_idx, ra); + case MO_BEQ: + return cpu_ldq_be_mmuidx_ra(env, taddr, mmu_idx, ra); + + default: + g_assert_not_reached(); + } +} + +static void tci_qemu_st(CPUArchState *env, target_ulong taddr, uint64_t val, + TCGMemOpIdx oi, const void *tb_ptr) +{ + uintptr_t ra = (uintptr_t)tb_ptr; + int mmu_idx = get_mmuidx(oi); + MemOp mop = get_memop(oi); + + switch (mop & (MO_BSWAP | MO_SIZE)) { + case MO_UB: + cpu_stb_mmuidx_ra(env, taddr, val, mmu_idx, ra); + break; + case MO_LEUW: + cpu_stw_le_mmuidx_ra(env, taddr, val, mmu_idx, ra); + break; + case MO_BEUW: + cpu_stw_be_mmuidx_ra(env, taddr, val, mmu_idx, ra); + break; + case MO_LEUL: + cpu_stl_le_mmuidx_ra(env, taddr, val, mmu_idx, ra); + break; + case MO_BEUL: + cpu_stl_be_mmuidx_ra(env, taddr, val, mmu_idx, ra); + break; + case MO_LEQ: + cpu_stq_le_mmuidx_ra(env, taddr, val, mmu_idx, ra); + break; + case MO_BEQ: + cpu_stq_be_mmuidx_ra(env, taddr, val, mmu_idx, ra); + break; + default: + g_assert_not_reached(); + } +} #if TCG_TARGET_REG_BITS == 64 # define CASE_32_64(x) \ @@ -906,34 +949,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, tci_args_rrrm(insn, &r0, &r1, &r2, &oi); taddr = tci_uint64(regs[r2], regs[r1]); } - switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) { - case MO_UB: - tmp32 = qemu_ld_ub; - break; - case MO_SB: - tmp32 = (int8_t)qemu_ld_ub; - break; - case MO_LEUW: - tmp32 = qemu_ld_leuw; - break; - case MO_LESW: - tmp32 = (int16_t)qemu_ld_leuw; - break; - case MO_LEUL: - tmp32 = qemu_ld_leul; - break; - case MO_BEUW: - tmp32 = qemu_ld_beuw; - break; - case MO_BESW: - tmp32 = (int16_t)qemu_ld_beuw; - break; - case MO_BEUL: - tmp32 = qemu_ld_beul; - break; - default: - g_assert_not_reached(); - } + tmp32 = tci_qemu_ld(env, taddr, oi, tb_ptr); regs[r0] = tmp32; break; @@ -949,46 +965,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, taddr = tci_uint64(regs[r3], regs[r2]); oi = regs[r4]; } - switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) { - case MO_UB: - tmp64 = qemu_ld_ub; - break; - case MO_SB: - tmp64 = (int8_t)qemu_ld_ub; - break; - case MO_LEUW: - tmp64 = qemu_ld_leuw; - break; - case MO_LESW: - tmp64 = (int16_t)qemu_ld_leuw; - break; - case MO_LEUL: - tmp64 = qemu_ld_leul; - break; - case MO_LESL: - tmp64 = (int32_t)qemu_ld_leul; - break; - case MO_LEQ: - tmp64 = qemu_ld_leq; - break; - case MO_BEUW: - tmp64 = qemu_ld_beuw; - break; - case MO_BESW: - tmp64 = (int16_t)qemu_ld_beuw; - break; - case MO_BEUL: - tmp64 = qemu_ld_beul; - break; - case MO_BESL: - tmp64 = (int32_t)qemu_ld_beul; - break; - case MO_BEQ: - tmp64 = qemu_ld_beq; - break; - default: - g_assert_not_reached(); - } + tmp64 = tci_qemu_ld(env, taddr, oi, tb_ptr); if (TCG_TARGET_REG_BITS == 32) { tci_write_reg64(regs, r1, r0, tmp64); } else { @@ -1005,25 +982,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, taddr = tci_uint64(regs[r2], regs[r1]); } tmp32 = regs[r0]; - switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) { - case MO_UB: - qemu_st_b(tmp32); - break; - case MO_LEUW: - qemu_st_lew(tmp32); - break; - case MO_LEUL: - qemu_st_lel(tmp32); - break; - case MO_BEUW: - qemu_st_bew(tmp32); - break; - case MO_BEUL: - qemu_st_bel(tmp32); - break; - default: - g_assert_not_reached(); - } + tci_qemu_st(env, taddr, tmp32, oi, tb_ptr); break; case INDEX_op_qemu_st_i64: @@ -1042,31 +1001,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, } tmp64 = tci_uint64(regs[r1], regs[r0]); } - switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) { - case MO_UB: - qemu_st_b(tmp64); - break; - case MO_LEUW: - qemu_st_lew(tmp64); - break; - case MO_LEUL: - qemu_st_lel(tmp64); - break; - case MO_LEQ: - qemu_st_leq(tmp64); - break; - case MO_BEUW: - qemu_st_bew(tmp64); - break; - case MO_BEUL: - qemu_st_bel(tmp64); - break; - case MO_BEQ: - qemu_st_beq(tmp64); - break; - default: - g_assert_not_reached(); - } + tci_qemu_st(env, taddr, tmp64, oi, tb_ptr); break; case INDEX_op_mb: -- 2.25.1