The following changes since commit 15106f7dc3290ff3254611f265849a314a93eb0e:
Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-hex-20210502' into staging (2021-05-02 16:23:05 +0100) are available in the Git repository at: g...@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210504-2 for you to fetch changes up to 7a98eab3a704139020bdad35bfae0356d2a31fa0: target/riscv: Fix the RV64H decode comment (2021-05-04 08:03:43 +1000) ---------------------------------------------------------------- A large collection of RISC-V fixes, improvements and features - Clenaup some left over v1.9 code - Documentation improvements - Support for the shakti_c machine - Internal cleanup of the CSR accesses - Updates to the OpenTitan platform - Support for the virtio-vga - Fix for the saturate subtract in vector extensions - Experimental support for the ePMP spec - A range of other internal code cleanups and bug fixes ---------------------------------------------------------------- Alexander Wagner (1): hw/riscv: Fix OT IBEX reset vector Alistair Francis (22): target/riscv: Convert the RISC-V exceptions to an enum target/riscv: Use the RISCVException enum for CSR predicates target/riscv: Fix 32-bit HS mode access permissions target/riscv: Use the RISCVException enum for CSR operations target/riscv: Use RISCVException enum for CSR access MAINTAINERS: Update the RISC-V CPU Maintainers hw/opentitan: Update the interrupt layout hw/riscv: Enable VIRTIO_VGA for RISC-V virt machine target/riscv: Fix the PMP is locked check when using TOR target/riscv: Add the ePMP feature target/riscv/pmp: Remove outdated comment target/riscv: Add ePMP support for the Ibex CPU target/riscv: Remove the hardcoded RVXLEN macro target/riscv: Remove the hardcoded SSTATUS_SD macro target/riscv: Remove the hardcoded HGATP_MODE macro target/riscv: Remove the hardcoded MSTATUS_SD macro target/riscv: Remove the hardcoded SATP_MODE macro target/riscv: Remove the unused HSTATUS_WPRI macro target/riscv: Remove an unused CASE_OP_32_64 macro target/riscv: Consolidate RV32/64 32-bit instructions target/riscv: Consolidate RV32/64 16-bit instructions target/riscv: Fix the RV64H decode comment Atish Patra (1): target/riscv: Remove privilege v1.9 specific CSR related code Axel Heider (1): docs/system/generic-loader.rst: Fix style Bin Meng (1): hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[] Dylan Jhong (1): target/riscv: Align the data type of reset vector address Emmanuel Blot (2): target/riscv: fix exception index on instruction access fault target/riscv: fix a typo with interrupt names Frank Chang (2): target/riscv: fix vrgather macro index variable type bug fpu/softfloat: set invalid excp flag for RISC-V muladd instructions Hou Weiying (4): target/riscv: Define ePMP mseccfg target/riscv: Add ePMP CSR access functions target/riscv: Implementation of enhanced PMP (ePMP) target/riscv: Add a config option for ePMP Jade Fink (1): riscv: don't look at SUM when accessing memory from a debugger context LIU Zhiwei (1): target/riscv: Fixup saturate subtract function Vijai Kumar K (5): target/riscv: Add Shakti C class CPU riscv: Add initial support for Shakti C machine hw/char: Add Shakti UART emulation hw/riscv: Connect Shakti UART to Shakti platform docs: Add documentation for shakti_c machine docs/system/generic-loader.rst | 9 +- docs/system/riscv/shakti-c.rst | 82 +++ default-configs/devices/riscv64-softmmu.mak | 1 + include/hw/char/shakti_uart.h | 74 +++ include/hw/riscv/opentitan.h | 16 +- include/hw/riscv/shakti_c.h | 75 +++ target/riscv/cpu.h | 42 +- target/riscv/cpu_bits.h | 114 +--- target/riscv/helper.h | 18 +- target/riscv/pmp.h | 14 + target/riscv/insn16-32.decode | 28 - target/riscv/insn16-64.decode | 36 -- target/riscv/insn16.decode | 30 + target/riscv/insn32-64.decode | 88 --- target/riscv/insn32.decode | 67 ++- hw/char/shakti_uart.c | 185 +++++++ hw/intc/ibex_plic.c | 20 +- hw/riscv/opentitan.c | 10 +- hw/riscv/shakti_c.c | 178 ++++++ hw/riscv/sifive_e.c | 2 +- target/riscv/cpu.c | 26 +- target/riscv/cpu_helper.c | 88 ++- target/riscv/csr.c | 824 +++++++++++++++++----------- target/riscv/fpu_helper.c | 16 +- target/riscv/gdbstub.c | 8 +- target/riscv/machine.c | 8 +- target/riscv/monitor.c | 22 +- target/riscv/op_helper.c | 18 +- target/riscv/pmp.c | 218 +++++++- target/riscv/translate.c | 38 +- target/riscv/vector_helper.c | 18 +- fpu/softfloat-specialize.c.inc | 6 + target/riscv/insn_trans/trans_rva.c.inc | 14 +- target/riscv/insn_trans/trans_rvd.c.inc | 17 +- target/riscv/insn_trans/trans_rvf.c.inc | 6 +- target/riscv/insn_trans/trans_rvh.c.inc | 8 +- target/riscv/insn_trans/trans_rvi.c.inc | 22 +- target/riscv/insn_trans/trans_rvm.c.inc | 12 +- target/riscv/insn_trans/trans_rvv.c.inc | 39 +- MAINTAINERS | 14 +- hw/char/meson.build | 1 + hw/char/trace-events | 4 + hw/riscv/Kconfig | 11 + hw/riscv/meson.build | 1 + target/riscv/meson.build | 13 +- target/riscv/trace-events | 3 + 46 files changed, 1755 insertions(+), 789 deletions(-) create mode 100644 docs/system/riscv/shakti-c.rst create mode 100644 include/hw/char/shakti_uart.h create mode 100644 include/hw/riscv/shakti_c.h delete mode 100644 target/riscv/insn16-32.decode delete mode 100644 target/riscv/insn16-64.decode delete mode 100644 target/riscv/insn32-64.decode create mode 100644 hw/char/shakti_uart.c create mode 100644 hw/riscv/shakti_c.c