On Wed, May 05, 2021 at 11:06:07AM +0200, Cédric Le Goater wrote: > Hello, > > The POWER10 DD2 CPU adds an extra LPCR[HAIL] bit which is a requirement > to support the scv instruction on PowerNV POWER10 platforms (glibc-2.33). > > These changes add a POWER10 DD2 CPU and switch the default chip model > of the powernv10 machine to use this CPU. This to make sure that the > machine can boot the latest distros.
LGTM as far as it goes. Couple of points
* I'd prefer to combine the two patches together, basically
atomically replacing DD1 with DD2
* I'd like to sort out the DAWR1 support first, or at the same time.
I think it's reasonable to treat anything about POWER10 emulation
as experimental and unstable until we put an actually publically
available chip in there. If we sort out DAWR1 support now, it
means we can avoid having another spapr capability flag to handle
the case of qemu versions that support DD2, but not DAWR1.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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