From: Khansa Butt <kha...@kics.edu.pk>
Signed-off-by: Khansa Butt <kha...@kics.edu.pk> --- target-mips/mips-defs.h | 2 ++ target-mips/translate_init.c | 24 ++++++++++++++++++++++++ 2 files changed, 26 insertions(+), 0 deletions(-) diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h index bf094a3..e1ec2b2 100644 --- a/target-mips/mips-defs.h +++ b/target-mips/mips-defs.h @@ -41,6 +41,7 @@ #define ASE_MICROMIPS 0x00080000 /* Chip specific instructions. */ +#define INSN_OCTEON 0x10000000 #define INSN_LOONGSON2E 0x20000000 #define INSN_LOONGSON2F 0x40000000 #define INSN_VR54XX 0x80000000 @@ -53,6 +54,7 @@ #define CPU_VR54XX (CPU_MIPS4 | INSN_VR54XX) #define CPU_LOONGSON2E (CPU_MIPS3 | INSN_LOONGSON2E) #define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F) +#define CPU_OCTEON (CPU_MIPS64R2 | INSN_OCTEON) #define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5) diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index c39138f..09d2605 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -451,6 +451,30 @@ static const mips_def_t mips_defs[] = .mmu_type = MMU_TYPE_R4000, }, { + .name = "octeon", + .CP0_PRid = 0x0d30, + .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | + (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | (63 << CP0C1_MMU) | + (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | + (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | + (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA), + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 0, + .SYNCI_Step = 32, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x36FBFFFF, + .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) | + (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | + (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV), + .SEGBITS = 49, + .PABITS = 49, + .insn_flags = CPU_OCTEON | ASE_MIPS3D, + .mmu_type = MMU_TYPE_R4000, + }, + { .name = "Loongson-2E", .CP0_PRid = 0x6302, /*64KB I-cache and d-cache. 4 way with 32 bit cache line size*/ -- 1.7.3.4