Hello Peter, I've been looking into adding support for Cortex-R4F.
1) Currently, -cpu is used to look up a Main ID Register value and to base feature decisions on that. This doesn't work for Cortex-R4 and Cortex-R4F, which have an identical MIDR but only -R4F has the FPU. Re-checking the model string, while ugly, does the trick. Comments? 2) The R4/R4F TRM says "It implements the ARMv7R architecture, and includes Thumb-2 technology" - how to incur the pre-v7 feature bits in addition to the easy _V7 and _THUMB2? I.e. where is it documented (in ARMv7-A/R TRM?) whether or not this should include _V4T, _V6K, etc.? If V7 were to always imply the same set of features, I would expect it alongside VAPA. (Could use some comments either way.) 3) How to handle processor revisions? The only two available TRMs for R4F seem to be r1p3 and r1p4. ARM_CPUID_CORTEXA9 seems to use r0p0, with r2p0 being the oldest available TRM atm. Apart from the actual MIDR define and its binding to -cpu name, this also affects the FPSID register and gets a little ugly with non-linear mappings. The ARM1136 seems a particularly bad example, will try to post a cleanup. Regards, Andreas Andreas Färber (2): target-arm: Prepare support for Cortex-R4 target-arm: Add support for Cortex-R4F target-arm/cpu.h | 1 + target-arm/helper.c | 49 +++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 50 insertions(+), 0 deletions(-) -- 1.7.3.4
