On Fri, 30 Apr 2021 at 22:17, Richard Henderson <richard.hender...@linaro.org> wrote: > > From: Stephen Long <stepl...@quicinc.com> > > Add decoding logic for SVE2 64-bit/32-bit gather non-temporal > load insns. > > 64-bit > * LDNT1SB > * LDNT1B (vector plus scalar) > * LDNT1SH > * LDNT1H (vector plus scalar) > * LDNT1SW > * LDNT1W (vector plus scalar) > * LDNT1D (vector plus scalar) > > 32-bit > * LDNT1SB > * LDNT1B (vector plus scalar) > * LDNT1SH > * LDNT1H (vector plus scalar) > * LDNT1W (vector plus scalar) > > Signed-off-by: Stephen Long <stepl...@quicinc.com> > Message-Id: <20200422152343.12493-1-stepl...@quicinc.com> > Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> thanks -- PMM
