This series adds support for the "Vector enhancements facility" and bumps the qemu CPU model to a stripped-down z14.
I tested most vector FP instructions by generating random instructions and vectors, comparing the result with results on actual hardware. I did not test instructions/instruction variants with (partial) undeterministic behavior and exception handling. Linux' also seems to boot/work fine with it. Howeever, while testing this series I noticed that Linux checks for the wrong facility bit - see [1]. I tested by temporarily faking availability of the "wrong" facility bit. [1] https://lkml.kernel.org/r/20210503121244.25232-1-da...@redhat.com v1 -> v2: - Too much changed to spell it out explicitly. Mostly addressed feedback from Richard, a couple of bugfixes found while testing, and some simplifications/cleanups. - Rebased on top of Richard's softfloat rework Based-on: 20210508014802.892561-1-richard.hender...@linaro.org Cc: qemu-s3...@nongnu.org Cc: Cornelia Huck <coh...@redhat.com> Cc: Halil Pasic <pa...@linux.ibm.com> Cc: Christian Borntraeger <borntrae...@de.ibm.com> Cc: Thomas Huth <th...@redhat.com> Cc: Richard Henderson <richard.hender...@linaro.org> David Hildenbrand (26): s390x/tcg: Fix FP CONVERT TO (LOGICAL) FIXED NaN handling s390x/tcg: Fix instruction name for VECTOR FP LOAD (LENGTHENED|ROUNDED) s390x/tcg: Simplify vop64_3() handling s390x/tcg: Simplify vop64_2() handling s390x/tcg: Simplify vfc64() handling s390x/tcg: Simplify vftci64() handling s390x/tcg: Simplify vfma64() handling s390x/tcg: Simplify vfll32() handling s390x/tcg: Simplify vflr64() handling s390x/tcg: Simplify wfc64() handling s390x/tcg: Implement VECTOR BIT PERMUTE s390x/tcg: Implement VECTOR MULTIPLY SUM LOGICAL s390x/tcg: Implement 32/128 bit for VECTOR FP (ADD|DIVIDE|MULTIPLY|SUBTRACT) s390x/tcg: Implement 32/128 bit for VECTOR (LOAD FP INTEGER|FP SQUARE ROOT) s390x/tcg: Implement 32/128 bit for VECTOR FP COMPARE * s390x/tcg: Implement 32/128 bit for VECTOR FP COMPARE (AND SIGNAL) SCALAR s390x/tcg: Implement 64 bit for VECTOR FP LOAD LENGTHENED s390x/tcg: Implement 128 bit for VECTOR FP LOAD ROUNDED s390x/tcg: Implement 32/128 bit for VECTOR FP PERFORM SIGN OPERATION s390x/tcg: Implement 32/128 bit for VECTOR FP TEST DATA CLASS IMMEDIATE s390x/tcg: Implement 32/128 bit for VECTOR FP MULTIPLY AND (ADD|SUBTRACT) s390x/tcg: Implement VECTOR FP NEGATIVE MULTIPLY AND (ADD|SUBTRACT) softfloat: Implement float128_(min|minnum|minnummag|max|maxnum|maxnummag) s390x/tcg: Implement VECTOR FP (MAXIMUM|MINIMUM) s390x/tcg: We support Vector enhancements facility s390x/cpumodel: Bump up QEMU model to a stripped-down IBM z14 GA2 fpu/softfloat.c | 17 + hw/s390x/s390-virtio-ccw.c | 3 + include/fpu/softfloat.h | 6 + target/s390x/cpu_models.c | 4 +- target/s390x/fpu_helper.c | 41 +- target/s390x/gen-features.c | 14 +- target/s390x/helper.h | 70 +- target/s390x/insn-data.def | 16 +- target/s390x/internal.h | 9 + target/s390x/translate_vx.c.inc | 633 ++++++++++++++---- target/s390x/vec_fpu_helper.c | 1114 ++++++++++++++++++++++--------- target/s390x/vec_helper.c | 22 + 12 files changed, 1478 insertions(+), 471 deletions(-) -- 2.31.1