On 20/05/2021 09:35, Stefan Hajnoczi wrote:
I realized I don't really understand how ISA IDE and PCI IDE interact in
PIIX3:
- ISA IDE has well-known PIO registers that are always present?
- PCI IDE has the same registers, but the BAR must be mapped and PCI IO
space access must be enabled?
- ISA IDE has a hardcoded ISA irq number?
- PCI IDE has a normal PCI irq that is routed like any legacy PCI INTx
irq?
- What combinations of ISA enabled/disabled and PCI enabled/disabled
need to be supported?
Yeah a lot of this discussion happened several months back in the Pegasos threads,
but here is my understanding:
- Older legacy PCI devices such as IDE controllers connected via a host containing a
PCI-ISA bridge can be switched by the guest OS into PCI legacy (also known as
compatibility mode) via a PCI config space register so that IO space accesses, IRQs
(and possible DMA?) are done via the ISA bus
- QEMU handles the IO memory accesses fine, since in these cases isa_bus_new() is
given the IO space by pci_address_space_io(dev) so IO space access generally "just works"
- Currently it is the responsibility of these older PCI devices to determine how they
have been configured and either use e.g. pci_set_irq() or qemu_raise_irq() on the ISA
IRQ for interrupts
- Generally ISA IRQs are fixed as per the old AT-style PCs so IDE would be 14/15
My thoughts above were about how to allow a PCIDevice to locate its ISABus if it is
connected to a bus with a PCI-ISA bridge to potentially allow access to ISA IRQs and
DMA if configured in PCI legacy mode.
ATB,
Mark.
