Hi Shashi, [ fixing my email address ]
On 5/13/21 4:25 PM, Shashi Mallela wrote: > Hi, > > Since the current SMMUv3 qemu implementation only supports stage 1 > translation,wanted to understand if the implementation could be extended > to stage 2 translation support and if yes what is the overall scope > involved.This is required for sbsa-ref platforms. Yes I think this is feasible. This would require some additionnal decoding in the STE and also adapt the page table decoding to stage2 according to AArch64 Virtual Memory System Architecture. If you proceed I would like this code to be isolated of the stage1 decoding as much as possible to alleviate the maintainance all the more so the stage1 code is the one likely to be used in production for DPDK or SVA use cases, let's dream. One of the tricky part is the internal TLB modeling (cache and IOTLB). In your case you may not need to implement such internal IOTLB for stage 2 entries as I guess you do not really target perf and this is the source of lots of bugs/headaches ;-) Thanks Eric > . > Thanks > Shashi > Sent from Mailspring