Based-on: <20210518201146.794854-1-richard.hender...@linaro.org> This commit attempts to implement a first draft of a solution to the first bug mentioned by Richard Henderson in this e-mail https://lists.nongnu.org/archive/html/qemu-devel/2021-05/msg06247.html The second bug was not touched, which is basically implementing the solution C
To sumarize the first bug here, from my understanding, when an address translation is asked of a 64bit mmu that uses hashtables, the code attempts to check some permission bits, but checks them from the wrong location. The solution implemented here is more complex than necessary on purpose, to make it more readable (and make sure I understand what is going on). If that would really fix the problem, I'll move to implementing an actual solution, and to all affected functions. Signed-off-by: Bruno Larsen (billionai) <bruno.lar...@eldorado.org.br> --- target/ppc/mmu-hash64.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index c1b98a97e9..63f10f1be7 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -887,6 +887,14 @@ bool ppc_hash64_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type, int exec_prot, pp_prot, amr_prot, prot; int need_prot; hwaddr raddr; + unsigned immu_idx, dmmu_idx; + immu_idx = (env->hflags >> HFLAGS_IMMU_IDX) & 7; + dmmu_idx = (env->hflags >> HFLAGS_DMMU_IDX) & 7; + const short HV = 1, IR = 2, DR = 3; + bool MSR[3]; + MSR[HV] = dmmu_idx & 2, + MSR[IR] = immu_idx & 4, + MSR[DR] = dmmu_idx & 4; /* * Note on LPCR usage: 970 uses HID4, but our special variant of @@ -897,7 +905,7 @@ bool ppc_hash64_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type, */ /* 1. Handle real mode accesses */ - if (access_type == MMU_INST_FETCH ? !msr_ir : !msr_dr) { + if (access_type == MMU_INST_FETCH ? !MSR[IR] : !MSR[DR]) { /* * Translation is supposedly "off", but in real mode the top 4 * effective address bits are (mostly) ignored @@ -909,7 +917,7 @@ bool ppc_hash64_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type, * In virtual hypervisor mode, there's nothing to do: * EA == GPA == qemu guest address */ - } else if (msr_hv || !env->has_hv_mode) { + } else if (MSR[HV] || !env->has_hv_mode) { /* In HV mode, add HRMOR if top EA bit is clear */ if (!(eaddr >> 63)) { raddr |= env->spr[SPR_HRMOR]; -- 2.17.1