See 'MicroBlaze Processor Reference Guide' UG081 (v9.0), Table 1-11: "Exception Status Register (ESR)".
Signed-off-by: Philippe Mathieu-Daudé <f4...@amsat.org> --- target/microblaze/cpu.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index e4bba8a7551..42b9ad8d313 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -95,10 +95,10 @@ typedef struct CPUMBState CPUMBState; #define ESR_EC_FPU 6 #define ESR_EC_PRIVINSN 7 #define ESR_EC_STACKPROT 7 /* Same as PRIVINSN. */ -#define ESR_EC_DATA_STORAGE 8 -#define ESR_EC_INSN_STORAGE 9 -#define ESR_EC_DATA_TLB 10 -#define ESR_EC_INSN_TLB 11 +#define ESR_EC_DATA_STORAGE 16 +#define ESR_EC_INSN_STORAGE 17 +#define ESR_EC_DATA_TLB 18 +#define ESR_EC_INSN_TLB 19 #define ESR_EC_MASK 31 /* Floating Point Status Register (FSR) Bits */ -- 2.26.3
