Add the isar feature check functions we will need for v8.1M MVE:
* a check for MVE present: this corresponds to the pseudocode's
CheckDecodeFaults(ExtType_Mve)
* a check for the optional floating-point part of MVE: this
corresponds to CheckDecodeFaults(ExtType_MveFp)
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20210520152840.24453-2-peter.mayd...@linaro.org
---
target/arm/cpu.h | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 04f8be35bf0..f1bd7d787cd 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3817,6 +3817,28 @@ static inline bool isar_feature_aa32_fp16_arith(const
ARMISARegisters *id)
}
}
+static inline bool isar_feature_aa32_mve(const ARMISARegisters *id)
+{
+ /*
+ * Return true if MVE is supported (either integer or floating point).
+ * We must check for M-profile as the MVFR1 field means something
+ * else for A-profile.
+ */
+ return isar_feature_aa32_mprofile(id) &&
+ FIELD_EX32(id->mvfr1, MVFR1, MVE) > 0;
+}
+
+static inline bool isar_feature_aa32_mve_fp(const ARMISARegisters *id)
+{
+ /*
+ * Return true if MVE is supported (either integer or floating point).
+ * We must check for M-profile as the MVFR1 field means something
+ * else for A-profile.
+ */
+ return isar_feature_aa32_mprofile(id) &&
+ FIELD_EX32(id->mvfr1, MVFR1, MVE) >= 2;
+}
+
static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id)
{
/*
--
2.20.1
