RISC-V define the hwcap as same as content of misa, but it only take lower 26-bits.
Signed-off-by: Kito Cheng <kito.ch...@sifive.com> --- linux-user/elfload.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 17ab06f612..41b9ef72ea 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -1433,6 +1433,17 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs, #define ELF_CLASS ELFCLASS64 #endif +#define ELF_HWCAP get_elf_hwcap() + +static uint32_t get_elf_hwcap(void) +{ + RISCVCPU *cpu = RISCV_CPU(thread_cpu); + /* Take lower 26 bits from misa. */ + uint32_t hwcap = cpu->env.misa & 0x3ffffff; + + return hwcap; +} + static inline void init_thread(struct target_pt_regs *regs, struct image_info *infop) { -- 2.31.1