On 6/7/21 9:57 AM, Peter Maydell wrote:
MVE has an FPSCR.QC bit similar to the A-profile Neon one; when MVE
is implemented make the bit writeable, both in the generic "load and
store FPSCR" helper functions and in the code for handling the NZCVQC
sysreg which we had previously left as "TODO when we implement MVE".
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
---
target/arm/translate-vfp.c | 32 +++++++++++++++++++++++---------
target/arm/vfp_helper.c | 3 ++-
2 files changed, 25 insertions(+), 10 deletions(-)
diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c
index d01e465821b..22a619eb2c5 100644
--- a/target/arm/translate-vfp.c
+++ b/target/arm/translate-vfp.c
@@ -784,10 +784,19 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int
regno,
{
TCGv_i32 fpscr;
tmp = loadfn(s, opaque);
- /*
- * TODO: when we implement MVE, write the QC bit.
- * For non-MVE, QC is RES0.
- */
+ if (dc_isar_feature(aa32_mve, s)) {
+ /* QC is only present for MVE; otherwise RES0 */
+ TCGv_i32 qc = tcg_temp_new_i32();
+ TCGv_i32 zero;
+ tcg_gen_andi_i32(qc, tmp, FPCR_QC);
+ store_cpu_field(qc, vfp.qc[0]);
+ zero = tcg_const_i32(0);
+ store_cpu_field(zero, vfp.qc[1]);
+ zero = tcg_const_i32(0);
+ store_cpu_field(zero, vfp.qc[2]);
+ zero = tcg_const_i32(0);
+ store_cpu_field(zero, vfp.qc[3]);
+ }
Ok I guess. You could store the same i32 into all elements:
tcg_gen_gvec_dup_i32(MO_32, offsetof(CPUARMState, vfp.qc),
16, 16, qc);
Either way,
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
r~
