On 09/06/2021 15:10, Philippe Mathieu-Daudé wrote:
(Added gitlab issue email)
Reposting Mark's patch:
https://www.mail-archive.com/qemu-devel@nongnu.org/msg814227.html
but split in 2 patches for easier review.
Mark Cave-Ayland (1):
cputlb: implement load_helper_unaligned() for unaligned loads
Philippe Mathieu-Daudé (1):
accel/tcg/cputlb: Extract load_helper_unaligned() from load_helper()
accel/tcg/cputlb.c | 106 ++++++++++++++++++++++++++++++++++++---------
1 file changed, 85 insertions(+), 21 deletions(-)
Thanks Phil. I'm replying to this to keep track of a few thoughts that came up in our
discussion on IRC:
- Should these unaligned accesses be handled by the memory API?
- There is an overlap with Andrew Jeffrey's unaligned access patchset for the memory
API at
http://patchwork.ozlabs.org/project/qemu-devel/patch/20170630030058.28943-1-and...@aj.id.au/.
This would certainly benefit devices which currently handle unaligned accesses
themselves.
- Currently there aren't any qtests to cover the unaligned access cputlb path
- How would using the memory API implementation interact with MemoryRegionOps
.valid.unaligned and .impl.unaligned?
- The current cputlb store_helper_unaligned() and also load_helper_unaligned()
proposed by this patchset always use byte accesses, i.e they do not honour the target
MemoryRegion min_access_size. Switching to the memory API could therefore cause some
existing cases to break, although -d guest_errors should now log these.
- Phil thinks that using the memory API could break ISA bus accesses
ATB,
Mark.
