Four "signed or unsigned 8 x signed or unsigned 8" with 32-bit addition
(32 = 32 + 8x8 + 8x8 + 8x8 + 8x8).
Signed-off-by: LIU Zhiwei <zhiwei_...@c-sky.com>
---
target/riscv/helper.h | 4 +++
target/riscv/insn32.decode | 4 +++
target/riscv/insn_trans/trans_rvp.c.inc | 5 +++
target/riscv/packed_helper.c | 44 +++++++++++++++++++++++++
4 files changed, 57 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 35c8c61b00..a0e3131512 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1326,3 +1326,7 @@ DEF_HELPER_2(clz32, tl, env, tl)
DEF_HELPER_2(clo32, tl, env, tl)
DEF_HELPER_3(pbsad, tl, env, tl, tl)
DEF_HELPER_4(pbsada, tl, env, tl, tl, tl)
+
+DEF_HELPER_4(smaqa, tl, env, tl, tl, tl)
+DEF_HELPER_4(umaqa, tl, env, tl, tl, tl)
+DEF_HELPER_4(smaqa_su, tl, env, tl, tl, tl)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index ce8bdee34b..96288370a6 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -929,3 +929,7 @@ clz32 1010111 11001 ..... 000 ..... 1110111 @r2
clo32 1010111 11011 ..... 000 ..... 1110111 @r2
pbsad 1111110 ..... ..... 000 ..... 1110111 @r
pbsada 1111111 ..... ..... 000 ..... 1110111 @r
+
+smaqa 1100100 ..... ..... 000 ..... 1110111 @r
+umaqa 1100110 ..... ..... 000 ..... 1110111 @r
+smaqa_su 1100101 ..... ..... 000 ..... 1110111 @r
diff --git a/target/riscv/insn_trans/trans_rvp.c.inc
b/target/riscv/insn_trans/trans_rvp.c.inc
index 43e7e5a75d..1a10f13318 100644
--- a/target/riscv/insn_trans/trans_rvp.c.inc
+++ b/target/riscv/insn_trans/trans_rvp.c.inc
@@ -511,3 +511,8 @@ GEN_RVP_R2_OOL(clz32);
GEN_RVP_R2_OOL(clo32);
GEN_RVP_R_OOL(pbsad);
GEN_RVP_R_ACC_OOL(pbsada);
+
+/* 8-bit Multiply with 32-bit Add Instructions */
+GEN_RVP_R_ACC_OOL(smaqa);
+GEN_RVP_R_ACC_OOL(umaqa);
+GEN_RVP_R_ACC_OOL(smaqa_su);
diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c
index 1f2b90c394..02178d6e61 100644
--- a/target/riscv/packed_helper.c
+++ b/target/riscv/packed_helper.c
@@ -2044,3 +2044,47 @@ static inline void do_pbsada(CPURISCVState *env, void
*vd, void *va,
}
RVPR_ACC(pbsada, 1, 1);
+
+/* 8-bit Multiply with 32-bit Add Instructions */
+static inline void do_smaqa(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+{
+ int8_t *a = va, *b = vb;
+ int32_t *d = vd, *c = vc;
+
+ d[H4(i)] = c[H4(i)] + a[H1(i * 4)] * b[H1(i * 4)] +
+ a[H1(i * 4 + 1)] * b[H1(i * 4 + 1)] +
+ a[H1(i * 4 + 2)] * b[H1(i * 4 + 2)] +
+ a[H1(i * 4 + 3)] * b[H1(i * 4 + 3)];
+}
+
+RVPR_ACC(smaqa, 1, 4);
+
+static inline void do_umaqa(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+{
+ uint8_t *a = va, *b = vb;
+ uint32_t *d = vd, *c = vc;
+
+ d[H4(i)] = c[H4(i)] + a[H1(i * 4)] * b[H1(i * 4)] +
+ a[H1(i * 4 + 1)] * b[H1(i * 4 + 1)] +
+ a[H1(i * 4 + 2)] * b[H1(i * 4 + 2)] +
+ a[H1(i * 4 + 3)] * b[H1(i * 4 + 3)];
+}
+
+RVPR_ACC(umaqa, 1, 4);
+
+static inline void do_smaqa_su(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+{
+ int8_t *a = va;
+ uint8_t *b = vb;
+ int32_t *d = vd, *c = vc;
+
+ d[H4(i)] = c[H4(i)] + a[H1(i * 4)] * b[H1(i * 4)] +
+ a[H1(i * 4 + 1)] * b[H1(i * 4 + 1)] +
+ a[H1(i * 4 + 2)] * b[H1(i * 4 + 2)] +
+ a[H1(i * 4 + 3)] * b[H1(i * 4 + 3)];
+}
+
+RVPR_ACC(smaqa_su, 1, 4);
--
2.25.1
