LIU Zhiwei <zhiwei_...@c-sky.com> 於 2021年4月9日 週五 下午3:52寫道：
> The interrupt-level threshold (xintthresh) CSR holds an 8-bit field
> for the threshold level of the associated privilege mode.
>
> For horizontal interrupts, only the ones with higher interrupt levels
> than the threshold level are allowed to preempt.
>
> Signed-off-by: LIU Zhiwei <zhiwei_...@c-sky.com>
>
Reviewed-by: Frank Chang <frank.ch...@sifive.com>
> ---
> target/riscv/cpu.h | 2 ++
> target/riscv/cpu_bits.h | 2 ++
> target/riscv/csr.c | 28 ++++++++++++++++++++++++++++
> 3 files changed, 32 insertions(+)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 1a44ca62c7..a5eab26a69 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -160,6 +160,7 @@ struct CPURISCVState {
>
> uint32_t miclaim;
> uint32_t mintstatus; /* clic-spec */
> + target_ulong mintthresh; /* clic-spec */
>
> target_ulong mie;
> target_ulong mideleg;
> @@ -173,6 +174,7 @@ struct CPURISCVState {
> target_ulong stvec;
> target_ulong sepc;
> target_ulong scause;
> + target_ulong sintthresh; /* clic-spec */
>
> target_ulong mtvec;
> target_ulong mepc;
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index c4ce6ec3d9..9447801d22 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -166,6 +166,7 @@
> #define CSR_MTVAL 0x343
> #define CSR_MIP 0x344
> #define CSR_MINTSTATUS 0x346 /* clic-spec-draft */
> +#define CSR_MINTTHRESH 0x347 /* clic-spec-draft */
>
> /* Legacy Machine Trap Handling (priv v1.9.1) */
> #define CSR_MBADADDR 0x343
> @@ -185,6 +186,7 @@
> #define CSR_STVAL 0x143
> #define CSR_SIP 0x144
> #define CSR_SINTSTATUS 0x146 /* clic-spec-draft */
> +#define CSR_SINTTHRESH 0x147 /* clic-spec-draft */
>
> /* Legacy Supervisor Trap Handling (priv v1.9.1) */
> #define CSR_SBADADDR 0x143
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 320b18ab60..4c31364967 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -746,6 +746,18 @@ static int read_mintstatus(CPURISCVState *env, int
> csrno, target_ulong *val)
> return 0;
> }
>
> +static int read_mintthresh(CPURISCVState *env, int csrno, target_ulong
> *val)
> +{
> + *val = env->mintthresh;
> + return 0;
> +}
> +
> +static int write_mintthresh(CPURISCVState *env, int csrno, target_ulong
> val)
> +{
> + env->mintthresh = val;
> + return 0;
> +}
> +
> /* Supervisor Trap Setup */
> static int read_sstatus(CPURISCVState *env, int csrno, target_ulong *val)
> {
> @@ -912,6 +924,18 @@ static int read_sintstatus(CPURISCVState *env, int
> csrno, target_ulong *val)
> return 0;
> }
>
> +static int read_sintthresh(CPURISCVState *env, int csrno, target_ulong
> *val)
> +{
> + *val = env->sintthresh;
> + return 0;
> +}
> +
> +static int write_sintthresh(CPURISCVState *env, int csrno, target_ulong
> val)
> +{
> + env->sintthresh = val;
> + return 0;
> +}
> +
> /* Supervisor Protection and Translation */
> static int read_satp(CPURISCVState *env, int csrno, target_ulong *val)
> {
> @@ -1666,9 +1690,13 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
>
> /* Machine Mode Core Level Interrupt Controller */
> [CSR_MINTSTATUS] = { "mintstatus", clic, read_mintstatus },
> + [CSR_MINTTHRESH] = { "mintthresh", clic, read_mintthresh,
> + write_mintthresh },
>
> /* Supervisor Mode Core Level Interrupt Controller */
> [CSR_SINTSTATUS] = { "sintstatus", clic, read_sintstatus },
> + [CSR_SINTTHRESH] = { "sintthresh", clic, read_sintthresh,
> + write_sintthresh },
>
> #endif /* !CONFIG_USER_ONLY */
> };
> --
> 2.25.1
>
>
>
