On 7/5/21 3:44 AM, Finn Thain wrote: > On Sun, 4 Jul 2021, Mark Cave-Ayland wrote: > >> Commit 3fe9a838ec "dp8393x: Always use 32-bit accesses" assumed that all >> accesses >> to the registers were 32-bit > > As I said, that assumption was not made there. > > If commit 3fe9a838ec is deficient it is probably because I am unaware of > the ability of the QEMU memory API to accomplish the desired result. > > That's not to say that the API can't do it, just that I don't know enough > about the API. > >> but this is actually not the case. The access size is determined by the >> CPU instruction used and not the number of physical address lines. >> > > Again, that is an over-simplification. To explain: in Apple hardware at > least, the access size that the SONIC chip sees is a consequence of bus > sizing logic that is not part of the CPU and is not part of the SONIC chip > either. > > AIUI, this logic is what Philippe alluded to when he said about this > patch, "This sounds to me like the 'QEMU doesn't model busses so we end > using kludge to hide bugs' pattern".
For the Jazz Magnum, the bus is partly represented in this datasheet: https://datasheet.datasheetarchive.com/originals/scans/Scans-054/DSAIH000102184.pdf I found the individual technical datasheet once, now I need to find them again :/ I'll try to implement the missing parts in the next dev cycle. Regards, Phil.